參數(shù)資料
型號(hào): ADS1601EVM
廠商: Texas Instruments
文件頁(yè)數(shù): 28/29頁(yè)
文件大?。?/td> 0K
描述: EVALUATION MODULE FOR ADS1601
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 1.25M
數(shù)據(jù)接口: 串行
輸入范圍: ±3 V
在以下條件下的電源(標(biāo)準(zhǔn)): 145mW @ 625kSPS,330mW @ 1.25MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: ADS1601
已供物品:
相關(guān)產(chǎn)品: 296-17631-6-ND - IC ADC 16BIT 1.25MSPS 48-TQFP
ADS1601IPFBTG4-ND - IC ADC 16BIT 1.25MSPS 48-TQFP
ADS1601IPFBRG4-ND - IC ADC 16BIT 1.25MSPS 48-TQFP
ADS1601IPFBR-ND - IC ADC 16BIT 1.25MSPS 48-TQFP
296-17631-1-ND - IC ADC 16BIT 1.25MSPS 48-TQFP
296-17631-2-ND - IC ADC 16BIT 1.25MSPS 48-TQFP
其它名稱: 296-17825
CLK
SYNC
t
SSC
t
HSC
FSO
t
C
t
SYPW
t
STL
CLK
FSO
t
CPW
SCLK
t
CS
t
CF
t
FPW
DOUT
t
DS
t
DH
MSB
BIT
14
LSB
NewData
BIT
1
t
CPW
SBAS322D
– DECEMBER 2004 – REVISED OCTOBER 2011
TIMING DIAGRAMS
Figure 1. Initialization Timing
TIMING REQUIREMENTS
For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tSYPW
SYNC positive pulse width
1
CLK period
tC
Clock period (CLK)
50
ns
tSSC
Setup time; SYNC rising edge to CLK rising edge
0.5
CLK period
tHSC
Hold time; CLK rising edge to SYNC falling edge
0.5
CLK period
Settling time of the ADS1601; FSO falling edge to next
tSTL
833
CLK periods
FSO rising edge
Figure 2. Data Retrieval Timing
TIMING REQUIREMENTS
For TA = –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tCS
Rising edge of CLK to rising edge of SCLK
15
ns
tCF
Rising edge of SCLK to rising edge of FSO
5
ns
tCPW
CLK positive or negative pulse width
25
ns
tFPW
Frame sync output high pulse width
1
CLK period
tDS
SCLK rising edge to new DOUT valid
5
ns
tDH
SCLK falling edge to DOUT invalid
20
ns
8
Copyright
2004–2011, Texas Instruments Incorporated
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