參數(shù)資料
型號(hào): ADS5102IPFB
廠商: Texas Instruments, Inc.
英文描述: 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
中文描述: 1.8 - V模擬電源,10位,65/40 MSPS的模擬到數(shù)字的,具有內(nèi)部參考變換器
文件頁(yè)數(shù): 8/23頁(yè)
文件大?。?/td> 334K
代理商: ADS5102IPFB
ADS5102
ADS5103
SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001
16
www.ti.com
PRINCIPLES OF OPERATION
analog input sample and hold amplifier circuit
The sample and hold amplifier is implemented using switch capacitor techniques. A simplified functional block
diagram is shown in Figure 29. The SHA is in sample mode when CLK is high and in hold mode when CLK is
low. In sample mode, the input switches, P1, are closed and the differential input signal is sampled onto caps
Cs. An internal common-mode voltage is applied to the sampling caps (Cs) when the two P1P switches are
closed. As the CLK falling edge occurs, the SHA is now placed into hold or amplification mode. In this mode,
P1 switches are now opened and switches P2 are closed. This is the amplification state and the signal is
transferred to the output of the amplifier with a nominal gain of 1. CL of Figure 29 represents the load
capacitance of the following stage. R-C values of the input determine the analog input bandwidth of the SHA
(and therefore the whole ADC) which is 950 MHz for the ADS5102/3. This wide bandwidth assures no distortion
to the Nyquist frequency of 32.5 MHz. In under sampling applications, it is common to require the analog input
bandwidth to be 5 times greater than the IF Nyquist frequency. As such, the ADS5102/3 supports IF frequencies
approaching 200 MHz in under sampling applications.
_
+ _
+
P1
CL
CI
P1P
VC
CS
P2
P1
VINP
VIN
Figure 29. Simplified Functional Block Diagram
Because the input to the sample and hold amplifier is a switched capacitor circuit, the input resistance is dynamic
and based on the sampling rate of the converter. The impedance of each input is defined by the equation:
Z
I +
1
F
Cs
Where:
Cs = Sampling capacitor = 0.4 pF typical
F = CLK frequency in Hz
The key for selecting an amplifier to correctly drive the ADS5102/3 is to ensure that the output frequency of the
amplifier is much lower than the input impedance of the ADS5102/3, which at 65 MSPS is 38.46 k
. For system
accuracy comparable to 1 LSB, this means selecting an amplifier with output impedance of ~ 31
for sampling
rates of 65 MSPS.
reference configurations
The ADS5102/3 provides an internal voltage reference which should be suitable for most 10 bit systems. The
typical full scale voltage for the device is determined by VFS = VREFT – VREFB. Since the input is fully
differential, the full scale input is twice the single ended value or 1 V differential. It is recommended to externally
de-couple both VREFT and VREFB with a 0.1
F capacitor to bypass all high frequency noise to ground. It is
necessary to connect BG and AVDD with a 100 k resistor and decouple with a 1 F capacitor to AGND (refer
to Figure 30 for correct configuration).
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ADS5103 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE
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