參數(shù)資料
型號: ADS6616A4A-7.5
廠商: ADATA Technology Co., Ltd.
英文描述: Synchronous DRAM(1M X 16 Bit X 4 Banks)
中文描述: 同步DRAM(1米× 16位× 4個銀行)
文件頁數(shù): 6/8頁
文件大小: 608K
代理商: ADS6616A4A-7.5
A-Data
ADS6616A4A
AC Characteristics
-5
-6
-7
-7.5
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit Note
/CAS Latency = 3 tCK3
5
6
7
7
System clock
Cycle time
/CAS Latency = 2 tCK2
7
1000
7.5
1000
8
1000
8
1000 ns
Clock high pulse width
tCHW
1.5
-
2
-
2
-
2
-
ns
1
Clock low pulse width
tCLW
1.5
-
2
-
2
-
2
-
ns
1
/CAS Latency = 3 tAC3
-
4.5
5
-
5.5
-
5.5
Access time
form clock
/CAS Latency = 2 tAC2
-
5.5
5.5
-
6
-
6
ns
2
Operation
tRC
54
-
60
-
65
-
65
-
/RAS cycle
time
Auto Refresh
tRRC
54
-
60
-
65
-
65
-
ns
/RAS to /CAS delay
tRCD
14
-
18
-
20
-
20
-
ns
/RAS active time
tRAS
40
100K
42
100K
42
120K
42
120K ns
/RAS precharge time
tRP
14
-
18
-
20
-
20
-
ns
/RAS to /RAS bank active delay
tRRD
10
-
12
-
14
-
14
-
ns
/CAS to /CAS delay
tCCD
1
-
1
-
1
-
1
-
CLK
Data – out hold time
tOH
1.5
-
2
-
2
-
2
-
ns
Data – input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Data – input hold time
tDH
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Address hold time
tAH
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
CKE hold time
tCKH
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
ns
1
Command hold time
tCH
1
-
1
-
1
-
1
-
ns
1
Refresh time
tREF
64
-
64
-
64
-
64
-
ms
Note :
1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.1 April, 2001
6
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