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參數資料
| 型號： | ADS7800KP |
| 英文描述： | Bus LVDS 2x2 Crosspoint/Repeater |
| 中文描述： | 12位為3ms采樣模擬到數字轉換器 |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 122K |
| 代理商： | ADS7800KP |
7
ADS7800
FIGURE 2. Basic
±
10V Operation.
OPERATION
BASIC OPERATION
Figure 2 shows the simple hookup circuit required to operate
the ADS7800 in a
±
10V range in the Convert Mode. A
convert command arriving on pin 19, R/C, (a pulse taking
pin 19 LOW for a minimum of 40ns) puts the ADS7800 in
the hold mode, and a conversion is started. Pin 21, BUSY,
will be held LOW during the conversion, and rises only after
the conversion is completed and the data has been trans-
ferred to the output latches. Thus, the rising edge of the
signal on pin 21 can be used to read the data from the
conversion. Also, during conversion, the BUSY signal puts
the output data lines in Hi-Z states and inhibits input lines.
This means that pulses on pin 19 are ignored, so that new
conversions cannot be initiated during a conversion, either
as a result of spurious signals or to short-cycle the
ADS7800.
In the Read Mode, the input to pin 19 is kept normally LOW,
and a HIGH pulse is used to read data and initiate a
conversion. In this mode, the rising edge of R/C on pin 19
will enable the output data pins, and the data from the
previous conversion becomes valid. The falling edge then
puts the ADS7800 in a hold mode, and initiates a new
conversion.
The ADS7800 will begin acquiring a new sample as soon
as the conversion is completed, even before the BUSY
output rises on pin 21, and will track the input signal until
the next conversion is started, whether in the Convert Mode
or the Read Mode.
THEORY OF OPERATION
The ADS7800 combines the advantages of advanced CMOS
technology (logic density, stable capacitors, and good
analog switches) with Burr-Brown’s proven skills in laser-
trimmed thin-film resistors to provide a complete sampling
A/D converter.
A basic charge-redistribution successive approximation
architecture converts analog input voltages into digital
words. Figure 1 shows the operation of a simplified three
bit charge redistribution A/D. Precision laser-trimmed
scaling resistors at the input divide standard input ranges
(
±
10V or
±
5V for the ADS7800) into levels compatible with
the CMOS characteristics of the internal capacitor array.
While in the sampling mode, the capacitor array switch for
the MSB capacitor (S
1
) is in position “S”, so that the charge
on the MSB capacitor is proportional to the voltage level of
the analog input signal, and the remaining array switches (S
2
and S
3
) are set to position “R” to provide an accurate bipolar
offset from the reference source REF. At the same time,
switch S
C
is also in the closed position to auto-zero any
offset errors in the CMOS comparator.
When a convert command is received, switch S
1
is opened
to trap a charge on the MSB capacitor proportional to the
input level at the time of the sampling command, switches
S
2
and S
3
are opened to trap an offset charge, and switch
S
C
is opened to float the comparator input. The charge
trapped on the capacitor array can now be moved between
the three capacitors in the array by connecting switches S
1
,
S
2
and S
3
to positions “R” (to connect to REF) or “G” (to
connect to GND) successively, changing the voltage gener-
ated at the comparator input node.
The first approximation connects the MSB capacitor via
switch S
1
to REF, while switches S
2
and S
3
are connected
to GND. Depending on whether the comparator output is
HIGH or LOW, the logic will then latch S
1
in position “R”
or “G”, and moves on to make the next approximation by
connecting S
2
to REF and S
3
to GND. When the three
successive approximation steps are made for this simple
converter, the voltage level at the comparator will be within
1/2LSB of GND, and the data output word will be based on
reading the positions of S
1
, S
2
and S
3
.
FIGURE 1. 3-Bit Charge Redistribution A/D.
G
R
S
S
1
G
R
S
2
G
R
S
3
+
–
L
o
g
i
c
Comparator
Out
To Switches
Ref
Signal
Input
S
C
4C
2C
C
IN 1
IN 2
REF
AGND
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
+5V
+5V
–15V
BUSY
CS
R/C
HBE
D0 (LSB)
D1
D2
D3
DGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
+
47μF
Input
Convert
Command
Busy
+
–15V
+
1μF
+5V
6.8μF
0.1μF
D11
(MSB)
D0
(LSB)
Data Out
相關PDF資料 |
PDF描述 |
|---|---|
| ADS7800AH | 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7800BH | 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7800JP | 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7800JU | 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7800KU | 12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADS7800KPG4 | 功能描述:模數轉換器 - ADC 12-Bit 3us Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7800KU | 功能描述:模數轉換器 - ADC 12-Bit 3us Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7800KU | 制造商:Texas Instruments 功能描述:12BIT ADC SAMPLING SMD SOIC24 |
| ADS7800KU/1K | 功能描述:模數轉換器 - ADC 12-Bit 3us Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7800KU/1KE4 | 功能描述:模數轉換器 - ADC 12-Bit 3us Sampling RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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