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參數(shù)資料
| 型號： | ADS7803 |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| 中文描述： | Autocalibrating，4通道，12位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 99K |
| 代理商： | ADS7803 |
9
ADS7803
PIN
FUNCTION
DESCRIPTION
D0
Mode Status
If LOW, Transparent Mode enabled for
data latches. If HIGH, latched Output
Mode enabled.
If HIGH, calibration cycle in progress.
If LOW, pin 26 used as input to initiate
calibration cycle. If HIGH, pin 26 used as
input to control sample-to-hold timing.
If HIGH, in Power Down Mode.
Reserved for factory use.
If HIGH, a power supply failure has
occurred. (Supply fell below 3V.)
If HIGH, an overflow occurred during
calibration.
If HIGH, conversion or calibration in
progress.
D1
D2
CAL Flag
Pin 26 Status
D3
D4
D5
Power Down Status
POWER FAIL Flag
D6
CAL ERROR Flag
D7
BUSY Flag
NOTE: These data are transferred to the bus when a read cycle is initiated
with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW
is reserved for factory use at this time, and will yield unpredictable data.
TABLE II. Reading the Special Function Register.
FIGURE 5. Writing to the SFR.
FIGURE 6. Reading the FSR.
POWER DOWN MODE
Writing a HIGH to D3 in the SFR puts the ADS7803 in the
Power Down Mode. Power consumption is reduced to 50
μ
W
and D3 remains HIGH. The internal clock and analog
circuitry are turned off, although the output registers and
SFR can still be accessed normally. To exit Power Down
Mode, either write a LOW to D3 in the SFR, or initiate a
calibration by sending a LOW to the CAL pin or writing
a HIGH to D1. Note that if the power supply falls below 3V
and then recovers, a calibration is automatically initiated,
and the SFR will be reset. D3 will be LOW, and the
ADS7803 will not be in the Power Down Mode.
During Power Down Mode, a pulse on CS and WR will
initiate a single conversion, then the ADS7803 will revert to
power down. Also, writing to D1 and D3 in the SFR will
initiate a calibration, do a single conversion and revert to the
Power Down Mode, in 185 clock cycles. Accurate conver-
sion results will be available in the output registers.
The activation delay from power down to normal operation
is included in the sampling time. No extra time is required,
either when coming out of the Power Down Mode or when
making a single conversion in the Power Down Mode.
OPERATION
CS/WR
SFR/HBE
D0
D1
D2
D3
D5
D4/D6/D7
Enables Transparent Mode for Data Latches
Enables Latched Output Mode for Data Latches
Initiates Calibration Cycle
Activates Sample/Hold Control Mode
Activates Power Down Mode
(2)
Resets Power Fail Flag
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
X
X
X
HIGH
(1)
X
X
HIGH
(1)
X
LOW
NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion,
then the ADS7803 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with
SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time.
TABLE III. Writing to the Special Function Register.
SAMPLE/HOLD CONTROL MODE
With D2 in the SFR HIGH, a rising edge input on pin 26 will
switch the ADS7803 from sample-mode to hold-mode with
a 5ns aperture delay. This also initiates a conversion, which
will start within 1.5 CLK cycles.
This mode allows full control over the sample-to-hold tim-
ing, which is especially useful where external events trigger
sampling timing.
In the Sample/Hold Control Mode, pin 26 must be held
LOW a minimum of 2.5
μ
s between conversions to allow
accurate acquisition of input signals. Also, offset error will
increase in this mode, since auto-zeroing of the comparator
is not synchronized to the sampling. Minimum offset is
achieved by synchronizing the sampling signal to CLK,
whether internal or external. Ideally, the sampling signal
D0 - D7
Valid Data
SFR
HBE
WR
CS
t
5
t
16
t
17
V
IL
V
IH
t
2
t
3
t
1
t
6
D0 - D7
SFR Data
SFR
HBE
RD
CS
t
11
t
14
V
IH
t
10
t
8
t
11
t
13
t
12
t
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7803BN | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7803BP | Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7807UBE4 | Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7807UBG4 | Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7807UE4 | Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7803BN | 制造商:BB 制造商全稱:BB 功能描述:Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7803BP | 制造商:BB 制造商全稱:BB 功能描述:Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER |
| ADS7804 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| ADS7804P | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 10us Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7804PB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 10us Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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