參數(shù)資料
型號： ADS7807PBG4
英文描述： Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER
中文描述： 低功耗，16位，采樣CMOS模擬數(shù)字轉換器
文件頁數(shù)： 10/24頁
文件大?。?/td> 534K
代理商： ADS7807PBG4
ADS7807
SBAS022C
10
www.ti.com
INTERNAL DATA CLOCK
(During a Conversion)
To use the internal data clock, tie
EXT/INT
(pin 8) LOW. The
combination of
R/C
(pin 22) and
CS
(pin 23) LOW will initiate
conversion
‘
n
’
and activate the internal data clock (typically
900kHz clock rate). The ADS7807 will output 16 bits of valid
data, MSB first, from conversion
‘
n-1
’
on SDATA (pin 19),
synchronized to 16 clock pulses output on DATACLK (pin 18).
The data will be valid on both the rising and falling edges of the
internal data clock. The rising edge of
BUSY
(pin 24) can be
used to latch the data. After the 16th clock pulse, DATACLK will
remain LOW until the next conversion is initiated, while SDATA
will go to whatever logic level was input on TAG (pin 20) during
the first clock pulse. Refer to Table VI and Figure 4.
EXTERNAL DATA CLOCK
To use an external data clock, tie
EXT/INT
(pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7807,
CS
(pin 23) must be LOW and
R/C
(pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion
‘
n
’
can be output on
SDATA (pin 19) after conversion
‘
n
’
is completed or during
conversion
‘
n + 1
’
.
An obvious way to simplify control of the converter is to tie
CS
LOW and use
R/C
to initiate conversions.
While this is perfectly acceptable, there is a possible problem
when using an external data clock. At an indeterminate point
from 12
μ
s after the start of conversion
‘
n
’
until
BUSY
rises,
the internal logic will shift the results of conversion
‘
n
’
into the
output register. If
CS
is LOW,
R/C
HIGH, and the external
clock is HIGH at this point, data will be lost. So, with
CS
LOW, either
R/C
and/or DATACLK must be LOW during this
period to avoid losing valid data.
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful with
the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these
pins will come out of Hi-Z state whenever
CS
(pin 23) is LOW
and
R/C
(pin 22) is HIGH. The serial output can not be tri-
stated and is always active. Refer to the Applications Infor-
mation section for specific serial interfaces.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
1
t
2
t
3
Convert Pulse Width
Data Valid Delay after
R/C
LOW
BUSY
Delay from
Start of Conversion
BUSY
LOW
BUSY
Delay after
End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Bus Relinquish Time
BUSY
Delay after Data Valid
Previous Data Valid
after Start of Conversion
Bus Access Time and BYTE Delay
Start of Conversion
to DATACLK Delay
DATACLK Period
Data Valid to DATACLK
HIGH Delay
Data Valid after DATACLK
LOW Delay
External DATACLK Period
External DATACLK LOW
External DATACLK HIGH
CS
and
R/C
to External
DATACLK Setup Time
R/C
to
CS
Setup Time
Valid Data after DATACLK HIGH
Throughput Time
0.04
12
20
85
μ
s
μ
s
ns
19
t
4
t
5
19
90
20
μ
s
ns
t
6
t
7
t
8
t
9
t
10
t
11
40
19
ns
μ
s
μ
s
ns
ns
μ
s
20
5
83
10
20
12
60
19
t
12
t
13
83
ns
μ
s
1.4
t
14
t
15
1.1
75
μ
s
ns
20
t
16
400
600
ns
t
17
t
18
t
19
t
20
100
40
50
25
ns
ns
ns
ns
t
21
t
22
10
25
ns
ns
μ
s
t
7
+ t
8
25
TABLE VI. Conversion and Data Timing. T
A
=
–
40
°
C to +85
°
C.
1
MSB Valid
CS or R/C
(1)
DATACLK
SDATA
BUSY
t
7
+ t
8
t
16
t
15
t
14
t
13
2
3
15
16
Bit 14 Valid
Bit 1 Valid
Bit 13 Valid
LSB Valid
1
MSB Valid
2
Bit 14 Valid
(Results from previous conversion.)
NOTE: (1) If controlling with
CS
, tie
R/C
LOW. Data bus pins will remain Hi-Z at all times.
If controlling with
R/C
, tie
CS
LOW. Data bus pins will be active when
R/C
is HIGH, and should be left unconnected.
相關PDF資料
PDF描述
ADS7807PG4 Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER
ADS7808UBE4 12-Bit 10us Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER
ADS7808UBG4 12-Bit 10us Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER
ADS7808UE4 12-Bit 10us Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER
ADS7809PB 16-Bit 10ms Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER
相關代理商/技術參數(shù)
參數(shù)描述
ADS7807PG4 功能描述:模數(shù)轉換器 - ADC Low-Power 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7807U 功能描述:模數(shù)轉換器 - ADC Low-Power 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7807U/1K 功能描述:模數(shù)轉換器 - ADC Low-Power 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7807U/1KE4 功能描述:模數(shù)轉換器 - ADC Low-Power 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7807U/1KG4 功能描述:模數(shù)轉換器 - ADC Low-Power 16-Bit Sampling CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*