Under normal operation, the REFOUT pin (pin 2)" />
參數(shù)資料
型號(hào): ADS8361IRHBT
廠商: Texas Instruments
文件頁數(shù): 2/29頁
文件大小: 0K
描述: IC ADC DUAL 16BIT 500KSPS 32VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 200mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 8 個(gè)單端,雙極;4 個(gè)差分,雙極
配用: 296-19922-ND - EVAL MOD FOR ADS8361
其它名稱: 296-17411-6
ADS8361
10
SBAS230E
www.ti.com
REFERENCE
Under normal operation, the REFOUT pin (pin 2) should be
directly connected to the REFIN pin (pin 1) to provide an
internal +2.5V reference to the ADS8361. The ADS8361 can
operate, however, with an external reference in the range of
1.2V to 2.6V for a corresponding full-scale range of 2.4V to
5.2V.
The internal reference of the ADS8361 is buffered. If the
internal reference is used to drive an external load, a buffer
is provided between the reference and the load applied to pin 2
(the internal reference can typically source 10μA of current—
load capacitance should be 0.1μF and 10μF). If an external
reference is used, the second buffer provides isolation be-
tween the external reference and the Capacitve Digital-to-
Analog Converter (CDAC). This buffer is also used to re-
charge all of the capacitors of both CDACs during conver-
sion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8361: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is
the (common-mode + VREF) and the (common-mode – VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or (+IN) – (–IN). The
peak-to-peak amplitude of each input is ±1/2 VREF around this
common voltage. However, since the inputs are 180° out-of-
phase, the peak-to-peak amplitude of the differential voltage is
+VREF to –VREF. The value of VREF also determines the range
of the voltage that may be common to both inputs (see
Figure 4).
INTRODUCTION
The ADS8361 is a high-speed, low-power, dual, 16-bit A/D
converter that operates from +3V/+5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual, 4μs successive
approximation A/D converter, two differential sample-and-
hold amplifiers, an internal +2.5V reference with REFIN and
REFOUT pins, and a high-speed serial interface. The ADS8361
requires an external clock. In order to achieve the maximum
throughput rate of 500kSPS, the master clock must be set at
10MHz. A minimum of 20 clock cycles are required for each
16-bit conversion.
There are four analog inputs that are grouped into two chan-
nels (A and B). Channel selection is controlled by the M0 (pin
14), M1 (pin 15), and A0 (pin 16) pins. Each channel has two
inputs (A0, A1 and B0, B1) that are sampled and converted
simultaneously, thus preserving the relative phase information
of the signals on both analog inputs. The part accepts an
analog input voltage in the range of –VREF to +VREF, centered
around the internal +2.5V reference. The part will also accept
bipolar input ranges when a level shift circuit is used at the front
end (see Figure 7).
All conversions are initiated on the ADS8361 by bringing the
CONVST pin HIGH for a minimum of 15ns. CONVST HIGH
places both sample-and-hold amplifiers in the hold state
simultaneously and the conversion process is started on both
channels. The RD pin (pin 18) can be connected to CONVST
to simplify operation. Depending on the status of the M0, M1,
and A0 pins, the ADS8361 will (a) operate in either two-
channel or four-channel mode and (b) output data on both
the Serial A and Serial B output or both channels can be
transmitted on the A output only.
NOTE: See the Timing and Control section of this data sheet
for more information.
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS8361 allow the
A/D converter to accurately convert an input sine wave of full-
scale amplitude to 16-bit accuracy. The input bandwidth of
the sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the A/D converter
even when the A/D converter is operated at its maximum
throughput rate of 500kSPS.
Typical aperture delay time, or the time it takes for the
ADS8361 to switch from the sample to the hold mode
following the CONVST pulse, is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS8361 to capture AC input signals accurately at the
exact same moment in time.
ADS8361
Single-Ended Input
Common
Voltage
–VREF to +VREF
peak-to-peak
Differential Input
Common
Voltage
VREF
peak-to-peak
VREF
peak-to-peak
FIGURE 1. Methods of Driving the ADS8361 Single-Ended or
Differential.
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