A = –40°C to 85°C, +VA = 5 V," />
參數(shù)資料
型號: ADS8412IPFBR
廠商: Texas Instruments
文件頁數(shù): 23/30頁
文件大小: 0K
描述: IC ADC 16BIT 2MSPS 48-TQFP
標準包裝: 1,000
位數(shù): 16
采樣率(每秒): 2M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 200mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
配用: 296-18385-ND - EVALUATION MODULE FOR ADS8412
www.ti.com
SPECIFICATIONS
ADS8412
SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
T
A = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage(1)
+IN – (–IN)
–Vref
Vref
V
+IN
–0.2
Vref + 0.2
Absolute input voltage
V
–IN
–0.2
Vref + 0.2
Common-mode input
ADS8412I
(Vref/2) – 0.2
Vref/2
(Vref/2) + 0.2
V
range
Input capacitance
25
pF
Input leakage current
0.5
nA
SYSTEM PERFORMANCE
Resolution
16
Bits
ADS8412I
15
No missing codes
Bits
ADS8412IB
16
ADS8412I
–6
±4
6
INL
Integral linearity (2)(3)
LSB
ADS8412IB
–2.5
±1.5
2.5
ADS8412I
–2
±1
3
DNL
Differential linearity
LSB
ADS8412IB
–1
±0.8
2
ADS8412I
–3
±1
3
EO
Offset error (4)
mV
ADS8412IB
–1.5
±0.5
1.5
ADS8412I
–0.15
0.15
EG
Gain error(4)(5)
%FS
ADS8412IB
–0.098
0.098
At dc (
±0.2 V around V
ref/2)
80
CMRR
Common-mode rejection ratio
dB
+IN – (–IN) = 1 Vpp at 1 MHz
80
Noise
60
V RMS
At 7FFFh output code,
PSRR
DC Power supply rejection ratio
+VA = 4.75 V to 5.25 V,
1
LSB
Vref = 4.096 V (4)
SAMPLING DYNAMICS
Conversion time
340
400
ns
Acquisition time
100
ns
Throughput rate
2
MHz
Aperture delay
2
ns
Aperture jitter
25
ps
Step response
100
ns
Overvoltage recovery
100
ns
DYNAMIC CHARACTERISTICS
VIN = 8 Vpp at 100 kHz
–95
THD
Total harmonic distortion(6)
dB
VIN = 8 Vpp at 500 kHz
–90
SNR
Signal-to-noise ratio
VIN = 8 Vpp at 100 kHz
90
dB
SINAD
Signal-to-noise + distortion
VIN = 8 Vpp at 100 kHz
88
VIN = 8 Vpp at 100 kHz
95
SFDR
Spurious free dynamic range
dB
VIN = 8 Vpp at 500 kHz
93
–3 dB Small signal bandwidth
5
MHz
(1)
Ideal input span, does not include gain or offset error.
(2)
LSB means least significant bit
(3)
This is endpoint INL, not best fit
(4)
Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V
(5)
This specification does not include the internal reference voltage error and drift.
(6)
Calculated on the first nine harmonics of the input frequency
3
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