參數(shù)資料
型號(hào)： ADSP-2101BP-100
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： ADSP-2100 Family DSP Microcomputers
中文描述： 24-BIT, 25 MHz, OTHER DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 32/64頁(yè)
文件大小： 666K
代理商： ADSP-2101BP-100
ADSP-21xx
–32–
REV. B
Frequency
Dependency
13 MHz
Min Max Min
13.824 MHz 16.67 MHz
Max
20 MHz
Min Max Min Max Min
25 MHz
Parameter
Min
Max
Max
Unit
Timing Requirement:
t
BH
BR Hold after CLKOUT High
1
t
BS
BR Setup before CLKOUT Low
1
39.2
Switching Characteristic:
t
SD
CLKOUT High to DMS,
PMS, BMS, RD, WR Disable
t
SDB
DMS, PMS, BMS, RD, WR
Disable to BG Low
t
SE
BG High to DMS, PMS,
BMS, RD, WR Enable
t
SEC
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
24.2
23.1
38.1
20
35
17.5
32.5
15
30
0.25t
CK
+ 5
0.25t
CK
+ 20
ns
ns
39.2
38.1
35
32.5
30
0.25t
CK
+ 20 ns
0
0
0
0
0
0
ns
0
0
0
0
0
0
ns
9.2
8.1
5
2.5
1.5
2
0.25t
CK
– 10
2
ns
NOTES
1
If BR meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
2
For 25 MHz only the minimum frequency dependency formula for t
SEC
= (0.25t
CK
– 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the
ADSP-2100 Family User’s Manual (1st Edition, 1993)
states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
TIMNGPARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS RE QUE ST /GRANT
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
t
BS
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
Figure 31. Bus Request/Grant
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