參數(shù)資料
型號(hào)： ADSP-2105
廠商： Analog Devices, Inc.
英文描述： ADSP-2100 Family DSP Microcomputers
中文描述： 的ADSP - 2100系列DSP的微機(jī)
文件頁數(shù)： 6/64頁
文件大?。?/td> 666K
代理商： ADSP-2105
ADSP-21xx
–6–
REV. B
of the ADSP-2111. T he two status registers provide status
information to both the ADSP-2111 and the host processor.
HSR7 contains a software reset bit which can be set by both the
ADSP-2111 and the host.
HIP transfers can be managed using either interrupts or polling.
T he HIP generates an interrupt whenever an HDR register
receives data from a host processor write. It also generates an
interrupt when the host processor has performed a successful
read of any HDR. T he read/write status of the HDRs is also
stored in the HSR registers.
T he HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the
HDR4 Write
bit in
HMASK and the
HIP Write
interrupt enable bit in IMASK are
set.
T he HIP provides a second method of booting the ADSP-2111
in which the host processor loads instructions into the HIP. T he
ADSP-2111 automatically transfers the data, in this case
opcodes, to internal program memory. T he BMODE pin
determines whether the ADSP-2111 boots from the host
processor through the HIP or from external EPROM over the
data bus.
Interrupts
T he ADSP-21xx’s interrupt controller lets the processor
respond to interrupts with a minimum of overhead. Up to three
external interrupt input pins,
IRQ0
,
IRQ1
, and
IRQ2
, are
provided.
IRQ2
is always available as a dedicated pin;
IRQ1
and
IRQ0
may be alternately configured as part of Serial Port 1. T he
ADSP-21xx also supports internal interrupts from the timer, the
serial ports, and the host interface port (on the ADSP-2111).
T he interrupts are internally prioritized and individually
maskable (except for
RESET
which is non-maskable). T he
IRQx
input pins can be programmed for either level- or edge-
sensitivity. T he interrupt priorities for each ADSP-21xx
processor are shown in T able III.
T he ADSP-21xx uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instruc-
tions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
T he interrupt control register, ICNT L, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNT L, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
Flexible Framing
—T he SPORT s have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
Different Word Lengths
—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware
—Each SPORT provides optional
A-law and
μ
-law companding according to CCIT T recommen-
dation G.711.
Flexible Interrupt Scheme
—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead
—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability
(SPORT 0 Only)
—SPORT 0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T 1 or CEPT
interfaces, or as a network communication scheme for multiple
processors. (Note that the ADSP-2105 includes only SPORT 1,
not SPORT 0, and thus does not offer multichannel operation.)
Alternate Configuration
—SPORT 1 can be alternatively
configured as two external interrupt inputs (
IRQ0
,
IRQ1
) and
the Flag In and Flag Out signals (FI, FO).
Host Interface Port (ADSP-2111)
T he ADSP-2111 includes a Host Interface Port (HIP), a
parallel I/O port that allows easy connection to a host processor.
T hrough the HIP, the ADSP-2111 can be accessed by the host
processor as a memory-mapped peripheral. T he host interface
port can be thought of as an area of dual-ported memory, or
mailbox registers, that allows communication between the
computational core of the ADSP-2111 and the host computer.
T he host interface port is completely asynchronous. T he host
processor can write data into the HIP while the ADSP-2111 is
operating at full speed.
T hree pins configure the HIP for operation with different types
of host processors. T he HSIZE pin configures HIP for 8- or 16-
bit communication with the host processor. HMD0 configures
the bus strobes, selecting either separate read and write strobes
or a single read/write select and a host data strobe. HMD1
selects either separate address (3-bit) and data (16-bit) buses or
a multiplexed 16-bit address/data bus with address latch enable.
T ying these pins to appropriate values configures the ADSP-
2111 for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
T he HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. T he HIP
data registers are memory-mapped in the internal data memory
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2105BP-55 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 13.824MHz 13.824MIPS 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:- Bulk
ADSP-2105BP-55REEL 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
ADSP-2105BP-80 功能描述:IC DSP CONTROLLER 16BIT 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-2105BP-80REEL 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 20MHZ 20MIPS - Tape and Reel
ADSP-2105BPZ-80 功能描述:IC DSP CONTROLLER 16BIT 68PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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