參數(shù)資料
型號: ADSP-21060KS-133
廠商: Analog Devices Inc
文件頁數(shù): 18/64頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 240MQFP
產(chǎn)品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,連接端口,串行端口
時鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 240-BFQFP 裸露焊盤
供應商設備封裝: 240-MQFP-EP(32x32)
包裝: 托盤
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 25 of 64
|
March 2008
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 14. Memory Read—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tDAD
Address Selects Delay to Data Valid1, 2
18 + DT + W
ns
tDRLD
RD Low to Data Valid1
12 + 5DT/8 + W
ns
tHDA
Data Hold from Address, Selects3
0.5
ns
tHDRH
Data Hold from RD High3
2.0
ns
tDAAK
ACK Delay from Address, Selects2, 4
14 + 7DT/8 + W
ns
tDSAK
ACK Delay from RD Low4
8 + DT/2 + W
ns
Switching Characteristics
tDRHA
Address Selects Hold After RD High
0 + H
ns
tDARL
Address Selects to RD Low2
2 + 3DT/8
ns
tRW
RD Pulse Width
12.5 + 5DT/8 + W
ns
tRWR
RD High to WR, RD, DMAGx Low
8 + 3DT/8 + HI
ns
tSADADC
Address, Selects Setup Before ADRCLK High2
0 + DT/4
ns
W = (number of wait states specified in WAIT register)
tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1 Data delay/setup: user must meet t
DAD or tDRLD or synchronous spec tSSDATI.
2 The falling edge of MSx, SW, BMS is referenced.
3 Data hold: user must meet t
HDA or tHDRH or synchronous spec tHSDATI. See Example System Hold Time Calculation on Page 47 for the calculation of hold times given capacitive
and dc loads.
4 ACK delay/setup: user must meet t
DAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK (high).
Figure 14. Memory Read—Bus Master
WR, DMAG
ACK
DATA
RD
ADDRESS
MSx, SW
BMS
tDARL
tRW
tDAD
tSADADC
tDAAK
tHDRH
tHDA
tRWR
tDRLD
ADRCLK
(OUT)
tDRHA
tDSAK
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