參數(shù)資料
型號: ADSP-21060LCB-133
廠商: Analog Devices Inc
文件頁數(shù): 28/64頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 225BGA
產品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,連接端口,串行端口
時鐘速率: 33MHz
非易失內存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 225-BBGA
供應商設備封裝: 225-PBGA
包裝: 托盤
Rev. F
|
Page 34 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Three-State Timing—Bus Master/ Bus Slave
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transi-
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS pin.
Table 21. Three-State Timing—Bus Master, Bus Slave
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSTSCK
SBTS Setup Before CLKIN
12 + DT/2
ns
tHTSCK
SBTS Hold Before CLKIN
6 + DT/2
ns
Switching Characteristics
tMIENA
Address/Select Enable After CLKIN1
–1.5 – DT/8
ns
tMIENS
Strobes Enable After CLKIN2
–1.5 – DT/8
ns
tMIENHG
HBG Enable After CLKIN
–1.5 – DT/8
ns
tMITRA
Address/Select Disable After CLKIN3
0 – DT/4
ns
tMITRS
Strobes Disable After CLKIN2
1.5 – DT/4
ns
tMITRHG
HBG Disable After CLKIN
2.0 – DT/4
ns
tDATEN
Data Enable After CLKIN4
9 + 5DT/16
ns
tDATTR
Data Disable After CLKIN4
0 – DT/8
7 – DT/8
ns
tACKEN
ACK Enable After CLKIN4
7.5 + DT/4
ns
tACKTR
ACK Disable After CLKIN4
–1 – DT/8
6 – DT/8
ns
tADCEN
ADRCLK Enable After CLKIN
–2 – DT/8
ns
tADCTR
ADRCLK Disable After CLKIN
8 – DT/4
ns
tMTRHBG
Memory Interface Disable Before HBG Low5
0 + DT/8
ns
tMENHBG
Memory Interface Enable After HBG High5
19 + DT
ns
1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min.
2 Strobes = RD, WR, PAGE, DMAG, BMS, SW.
3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max.
4 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
5 Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).
Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
MEMORY
INTERFACE
HBG
MEMORY INTERFACE = ADDRESS,
RD, WR, MSx, SW,PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
tMENHBG
tMTRHBG
相關PDF資料
PDF描述
VI-B4Z-CY-F2 CONVERTER MOD DC/DC 2V 20W
ATFC-0402-1N2-BT INDUCTOR THIN FILM 1.2NH 0402
ADSP-21060LAB-160 IC DSP CONTROLLER 32BIT 225BGA
REC3-1215DRW/H/B CONV DC/DC 3W 9-18VIN +/-15VOUT
TAJY107K016A CAP TANT 100UF 16V 10% 2917
相關代理商/技術參數(shù)
參數(shù)描述
ADSP-21060LCBZ-133 功能描述:IC DSP CONTROLLER 32BIT 225PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI,以太網(wǎng),RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應商設備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21060LCW-133 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 33MHz 33MIPS 240-Pin CQFP 制造商:Rochester Electronics LLC 功能描述:SHARC IND.,3V,33MHZ CQFP HEAT SLUG DOWN - Bulk
ADSP-21060LCW-160 功能描述:IC DSP CONTROLLER 32BIT 240CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI,以太網(wǎng),RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應商設備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21060LCWZ-133 制造商:Analog Devices 功能描述:SHARC INDUSTRIAL 5V CQFP HEAT SLUG UP - Trays
ADSP-21060LCWZ-160 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 40MHz 40MIPS 240-Pin CQFP 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 40MHZ 40MIPS 240CQFP - Trays 制造商:Analog Devices 功能描述:IC DSP SHARC 32BIT 40MHZ CQFP240