參數(shù)資料
型號(hào)： ADSP-2115BP-80
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： ADSP-2100 Family DSP Microcomputers
中文描述： 24-BIT, 20 MHz, OTHER DSP, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 19/64頁(yè)
文件大?。?/td> 666K
代理商： ADSP-2115BP-80
ADSP-21xx
REV. B
–19–
POWE R DISSIPAT ION E X AMPLE
T o determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
×
V
DD
2
×
f
C
= load capacitance,
f
= output switching frequency.
E xample:
In an ADSP-2101 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
T he application operates at V
DD
= 5.0 V and t
CK
= 50 ns.
Total Power Dissipation
=
P
INT
+
(C
×
V
DD2
×
f
)
P
INT
= internal power dissipation (from Figure 11).
(
C
×
V
DD2
×
f
) is calculated for each output:
# of
Pins
×
C
Output
×
V
DD2
×
f
Address,
DMS
8
Data,
WR
RD
CLK OUT
×
10 pF
×
10 pF
×
10 pF
×
10 pF
×
5
2
V
×
5
2
V
×
5
2
V
×
5
2
V
×
20 MHz = 40.0 mW
×
10 MHz = 22.5 mW
×
10 MHz = 2.5 mW
×
20 MHz = 5.0 mW
9
1
1
70.0 mW
T otal power dissipation for this example = P
INT
+ 70.0 mW.
E NVIRONME NT AL CONDIT IONS
Ambient T emperature Rating:
T
AMB
= T
CASE
– (PD
×
θ
C A
)
T
CASE
= Case T emperature in
°
C
PD = Power Dissipation in W
θ
C A
= T hermal Resistance (Case-to-Ambient)
θ
JA
= T hermal Resistance (Junction-to-Ambient)
θ
JC
= T hermal Resistance (Junction-to-Case)
Package
θ
JA
θ
JC
θ
CA
PGA
PLCC
PQFP
T QFP
18
°
C/W
27
°
C/W
60
°
C/W
60
°
C/W
9
°
C/W
16
°
C/W
18
°
C/W
18
°
C/W
9
°
C/W
11
°
C/W
42
°
C/W
42
°
C/W
SPECIFICATIONS(ADSP-2101/2105/2115/2161/2163)
CAPACIT IVE LOADING
Figures 12 and 13 show capacitive loading characteristics for the
ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2161/2163.
C
L
– pF
25
150
125
100
75
50
R
V
DD
= 4.5V
8
7
6
5
4
3
2
1
0
175
0
Figure 12. Typical Output Rise Time vs. Load Capacitance, C
L
(at Maximum Ambient Operating Temperature)
Figure 13. Typical Output Valid Delay or Hold vs. Load
Capacitance, C
L
(at Maximum Ambient Operating Temperature)
C
L
– pF
25
100
125
50
75
150
V
V
DD
= 4.5V
175
0
5
4
3
2
1
0
–1
–2
–3
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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