參數(shù)資料
型號: ADSP-2115BS-66
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: ADSP-2100 Family DSP Microcomputers
中文描述: 24-BIT, 16.67 MHz, OTHER DSP, PQFP80
封裝: METRIC, PLASTIC, QFP-80
文件頁數(shù): 46/64頁
文件大?。?/td> 666K
代理商: ADSP-2115BS-66
ADSP-21xx
–46–
REV. B
TIMNGPARAMETERS (ADSP-2103/2162/2164)
INT E RRUPT S & FLAGS
Frequency
Dependency
Min
10.24 MHz
Min
Parameter
Max
Max
Unit
Timing Requirement:
t
IFS
IRQx
1
or FI Setup before CLKOUT Low
2, 3
t
IFH
IRQx
1
or FI Hold after CLKOUT High
2, 3
Switching Characteristic:
t
FOH
FO Hold after CLKOUT High
t
FOD
FO Delay from CLKOUT High
44.4
24.4
0.25t
CK
+ 20
0.25t
CK
ns
ns
0
ns
ns
15
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2
.
2
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the
ADSP-2100 Family User’s Manual
for further information on
interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
FLAG
OUTPUT(S)
t
FOD
IRQ
x
FI
t
FOH
t
IFH
t
IFS
Figure 40. Interrupts & Flags
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