參數(shù)資料
型號: ADSP-21364SKBCZENG
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝: LEAD FREE, MO-205AE, MBGA-136
文件頁數(shù): 32/52頁
文件大?。?/td> 853K
代理商: ADSP-21364SKBCZENG
Rev. PrB
|
Page 32 of 52
|
September 2004
ADSP-21364
Preliminary Technical Data
Input Data Port (IDP)
The timing requirements for the IDP are given in
Table 28
.IDP
Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 28. IDP
Parameter
Timing Requirements
t
SIFS
1
t
SIHFS
1
t
SISD
1
t
SIHD
1
t
IDPCLKW
t
IDPCLK
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
Min
Max
Unit
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
2.5
2.5
2.5
2.5
9
24
ns
ns
ns
ns
ns
ns
Figure 23. IDP Master Timing
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
SAMPLE EDGE
t
SISD
t
SIHD
t
SISFS
t
SIHFS
t
SISCLKW
DAI_P20-1
(SDATA)
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