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參數(shù)資料
| 型號(hào)： | ADSP-21477BCPZ-1A |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 62/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARK 200MHZ 88LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，I²C，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 200MHz |
| 芯片上RAM： | 2Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤(pán) |
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Rev. C
|
Page 65 of 76
|
July 2013
OUTPUT DRIVE CURRENTS
Table 56 shows the driver types and the pins associated with
each driver. Figure 47 shows typical I-V characteristics for each
driver. The curves represent the current drive capability of the
output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 21 on Page 29 through Table 55 on Page 64. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 48.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 49. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
how output delays and holds vary with load capacitance. The
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
Table 56. Driver Types
Driver Type
Associated Pins
A
FLAG[0–3], AMI_ADDR[23–0], DATA[15–0],
AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,
SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU,
TDO, RESETOUT, DPI[1–14], DAI[1–20],
WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO,
MLBCLK, SR_CLR, SR_LAT, SR_LDO[17–0],
SR_SCLK, SR_SDI
BSDCLK, RTCLKOUT
Figure 47. Typical Drive at Junction Temperature
SWEEP (V
DDEXT) VOLTAGE (V)
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
100
200
SOURCE/SINK
(V
DDEXT
)CURRENT
(mA)
150
50
-100
-200
-150
-50
V
OH 3.13 V, 125 °C
V
OL 3.13 V, 125 °C
TYPE A
TYPE B
Figure 48. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 49. Voltage Reference Levels for AC Measurements
Figure 50. Typical Output Rise/Fall Time (20% to 80%,
VDD_EXT = Max)
T1
ZO = 50
(impedance)
TD = 4.04
r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
0.5pF
70
400
45
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
INPUT
OR
OUTPUT
1.5V
LOAD CAPACITANCE (pF)
6
0
7
4
2
1
3
RISE
AND
FALL
TIMES
(ns)
125
200
100
25
175
50
75
150
5
y = 0.0331x + 0.2662
y = 0.0184x + 0.3065
y = 0.0421x + 0.2418
y = 0.0206x + 0.2271
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE FALL
TYPE B DRIVE RISE
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