參數(shù)資料
型號: ADSP-2162BP-40
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputers with ROM
中文描述: 24-BIT, 10.24 MHz, OTHER DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 30/39頁
文件大?。?/td> 243K
代理商: ADSP-2162BP-40
REV. 0
ADSP-216x
–30–
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
INTERRUPTS AND FLAGS
Frequency
Dependency
Min
10.24 MHz
Min
13.0 MHz
Min
16.67 MHz
Min
Parameter
Max
Max
Max
Max
Unit
Timing Requirements:
t
IFS
IRQx
1
or FI Setup Before
CLKOUT Low
2, 3
t
IFH
IRQx
1
or FI Hold After
CLKOUT High
2, 3
Switching Characteristics:
t
FOH
FO Hold After CLKOUT High
t
FOD
FO Delay from CLKOUT High
44.4
39.2
35.0
0.25t
CK
+ 20
ns
24.4
19.2
15.0
0.25t
CK
ns
0
0
0
0
ns
ns
15
15
15
15
NOTES
1
IRQx
=
IRQ0
,
IRQ1
, and
IRQ2
.
2
If
IRQx
and FI inputs meet t
and t
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the
ADSP-2100 Family User’s Manual
, Third Edition,
for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
t
FOH
CLKOUT
FLAG
OUTPUT(S)
IRQx
FI
t
IFS
t
IFH
t
FOD
Figure 28. Interrupts and Flags
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