V
參數(shù)資料
型號： ADSP-2186MKCAZ-300
廠商： Analog Devices Inc
文件頁數(shù)： 10/40頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點
接口： 主機(jī)接口，串行端口
時鐘速率： 75MHz
非易失內(nèi)存： 外部
芯片上RAM： 40kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-迷你型BGA
包裝： 托盤
REV. 0
–18–
ADSP-2186M–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
VDDINT
2.37
2.63
2.25
2.75
V
VDDEXT
2.37
3.6
2.25
3.6
V
VINPUT
1
VIL = –0.3
VIH = +3.6
VIL = –0.3
VIH = +3.6
V
TAMB
0
+70
–40
+85
°C
NOTES
1The ADSP-2186M is 3.3 V tolerant (always accepts up to 3.6 V max V
IH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT; because VOH (max)
≈ V
DDEXT (max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS 0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET,
BR, DR0, DR1, PWD).
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter
Test Conditions
Min
Typ
Max
Unit
VIH
Hi-Level Input Voltage
1, 2
@ VDDINT = max
1.5
V
VIH
Hi-Level CLKIN Voltage
@ VDDINT = max
2.0
V
VIL
Lo-Level Input Voltage
1, 3
@ VDDINT = min
0.7
V
VOH
Hi-Level Output Voltage
1, 4, 5
@ VDDEXT = min, IOH = –0.5 mA
2.0
V
@ VDDEXT = 3.0 V, IOH = –0.5 mA
2.4
V
@ VDDEXT = min, IOH = –100
A6
VDDEXT – 0.3
V
VOL
Lo-Level Output Voltage
1, 4, 5
@ VDDEXT = min, IOL = 2 mA
0.4
V
IIH
Hi-Level Input Current3
@ VDDINT = max, VIN = 3.6 V
10
A
IIL
Lo-Level Input Current
3
@ VDDINT = max, VIN = 0 V
10
A
IOZH
Three-State Leakage Current
7
@ VDDEXT = max, VIN = 3.6 V
8
10
A
IOZL
Three-State Leakage Current7
@ VDDEXT = max, VIN = 0 V
8
10
A
IDD
Supply Current (Idle)
9
@ VDDINT = 2.5, tCK = 15 ns
9
mA
IDD
Supply Current (Idle)
9
@ VDDINT = 2.5, tCK = 13.3 ns
10
mA
IDD
Supply Current (Dynamic)
10
@ VDDINT = 2.5, tCK = 15 ns
11, T
AMB = 25
°C35
mA
IDD
Supply Current (Dynamic)
10
@ VDDINT = 2.5, tCK = 13.3 ns
11, T
AMB = 25
°C38
mA
IDD
Supply Current (Power-Down)
12
@ VDDINT = 2.5, TAMB = 25
°C in Lowest
100
A
Power Mode
CI
Input Pin Capacitance
3, 6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25
°C8
pF
CO
Output Pin Capacitance
6, 7, 12, 13
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25
°C8
pF
NOTES
1 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2 Input only pins:
RESET, BR, DR0, DR1, PWD.
3 Input only pins: CLKIN,
RESET, BR, DR0, DR1, PWD.
4 Output pins:
BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5 Although specified for TTL outputs, all ADSP-2186M outputs are CMOS-compatible and will drive to V
DDEXT and GND, assuming no dc loads.
6 Guaranteed but not tested.
7 Three-statable pins: A0–A13, D0–D23,
PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8 0 V on
BR.
9 Idle refers to ADSP-2186M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD or GND.
10 I
DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.
11 V
IN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12 See Chapter 9 of the ADSP-2100 Family User’s Manual for details.
13 Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
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