Rev. C
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Page 42 of 48
|
May 2009
ADSP-TS101S
AA1
DATA46
AB1
DATA49
AC1
VSS
AD1
VSS
AE1
VSS
AA2
DATA45
AB2
DATA48
AC2
VSS
AD2
VSS
AE2
VSS
AA3
DATA44
AB3
DATA47
AC3
DATA50
AD3
VSS
AE3
VSS
AA4
VDD_IO
AB4
VDD_IO
AC4
DATA51
AD4
DATA52
AE4
DATA53
AA5
VDD_IO
AB5
VDD_IO
AC5
DATA54
AD5
DATA55
AE5
DATA56
AA6
VDD_IO
AB6
VDD_IO
AC6
DATA57
AD6
DATA58
AE6
DATA59
AA7
VDD
AB7
VDD_IO
AC7
DATA60
AD7
DATA61
AE7
DATA62
AA8
VDD
AB8
VDD_IO
AC8
DATA63
AD8
L2DAT0
AE8
L2DAT1
AA9
VDD_IO
AB9
VDD_IO
AC9
L2DAT2
AD9
L2DAT3
AE9
L2DAT4
AA10
VDD_IO
AB10
VDD_IO
AC10
L2DAT5
AD10
L2DAT6
AE10
L2DAT7
AA11
VDD
AB11
VDD_IO
AC11
L2CLKOUT
AD11
L2CLKIN
AE11
L2DIR
AA12
VDD
AB12
VDD_IO
AC12
NC
AD12
BR0
AE12
BR1
AA13
VDD_IO
AB13
VDD_IO
AC13
BR2
AD13
BR3
AE13
BR4
AA14
VDD_IO
AB14
VDD_IO
AC14
BR5
AD14
BR6
AE14
BR7
AA15
VDD
AB15
VDD_IO
AC15
ACK
AD15
HBR
AE15
BOFF
AA16
VDD
AB16
VDD_IO
AC16
HBG
AD16
CPA
AE16
DPA
AA17
VDD_IO
AB17
VDD_IO
AC17
ADDR0
AD17
ADDR1
AE17
ADDR2
AA18
VDD_IO
AB18
VDD_IO
AC18
ADDR3
AD18
ADDR4
AE18
ADDR5
AA19
VDD
AB19
VDD_IO
AC19
ADDR6
AD19
ADDR7
AE19
ADDR8
AA20
VDD
AB20
VDD_IO
AC20
ADDR9
AD20
SDA10
AE20
ADDR10
AA21
VDD_IO
AB21
VDD_IO
AC21
ADDR11
AD21
ADDR12
AE21
ADDR13
AA22
VDD_IO
AB22
VDD_IO
AC22
ADDR14
AD22
ADDR15
AE22
VSS
AA23
ADDR23
AB23
ADDR20
AC23
VSS
AD23
VSS
AE23
VSS
AA24
ADDR22
AB24
ADDR19
AC24
ADDR17
AD24
VSS
AE24
VSS
AA25
ADDR21
AB25
ADDR18
AC25
ADDR16
AD25
VSS
AE25
VSS
Figure 42. 625-Ball PBGA Pin Configurations (Top View, Summary)
Table 36. 625-Ball (27 mm 27 mm) PBGA Pin Assignments (Continued)
Pin No.
Mnemonic
Pin No.
Mnemonic
Pin No.
Mnemonic
Pin No.
Mnemonic
Pin No.
Mnemonic
TOP VIEW
19
17
21
23
25
15
13
11
9
57
3
1
20
18
16
14
12
10
8
6
24
22
24
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Y
W
V
U
T
AE
AD
AC
AB
AA
VDD
VDD_IO
VSS
SIGNAL
VDD_A
VSS_A
KEY: