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參數(shù)資料
| 型號： | ADT7461AR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 【1∑C Temperature Monitor with Series Resistance Cancellation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MS-012-AA, SOIC-8 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 854K |
| 代理商： | ADT7461AR-REEL |
ADT7461
Reading the status register will clear the five flags, Bits 6–2,
provided the error conditions that caused the flags to be set
have gone away. A flag bit can only be reset if the corresponding
value register contains an in-limit measurement or if the sensor
is good.
The ALERT interrupt latch is not reset by reading the status
register. It will be reset when the ALERT output has been
serviced by the master reading the device address, provided the
error condition has gone away and the status register flag bits
have been reset.
When Flag 1 and/or Flag 0 are set, the THERM output goes low
to indicate that the temperature measurements are outside the
programmed limits. The THERM output does not need to be
reset, unlike the ALERT output. Once the measurements are
within the limits, the corresponding status register bits are reset
automatically, and the THERM output goes high. The user may
add hysteresis by programming Register 0×21. The THERM
output will be reset only when the temperature falls to limit
value–hysteresis value.
When Pin 6 is configured as THERM2, only the high tempera-
ture limits are relevant. If Flag 6 and/or Flag 4 are set, the
THERM2 output goes low to indicate that the temperature
measurements are outside the programmed limits. Flag 5 and
Flag 3 have no effect on THERM2. The behavior of THERM2 is
otherwise the same as THERM.
Table 9. Status Register Bit Assignments
Bit Name
Function
7
BUSY
1 When ADC Converting
6
LHIGH*
1 When Local High Temperature Limit Tripped
5
LLOW*
1 When Local Low Temperature Limit Tripped
4
RHIGH*
1 When Remote High Temperature Limit Tripped
3
RLOW*
1 When Remote Low Temperature Limit Tripped
2
OPEN*
1 When Remote Sensor Open Circuit
1
RTHRM
1 When Remote THERM Limit Tripped
0
LTHRM
1 When Local THERM Limit Tripped
*These flags stay high until the status register is read, or they are reset by POR.
Offset Register
Offset errors may be introduced into the remote temperature
measurement by clock noise or by the thermal diode being
located away from the hot spot. To achieve the specified accu-
racy on this channel, these offsets must be removed.
The offset value is stored as a 10-bit, twos complement value in
Registers 0×11 (high byte) and 0×12 (low byte, left justified).
Only the upper 2 bits of register 0×12 are used. The MSB of
Register 0×11 is the sign bit. The minimum offset that can be
programmed is 128°C, and the maximum is +127.75°C. The
value in the offset register is added or subtracted to the meas-
ured value of the remote temperature.
The offset register powers up with a default value of 0°C and
will have no effect unless the user writes a different value to it.
Table 10. Sample Offset Register Codes
Offset Value
0×11
128°C
1000 0000
4°C
1111 1100
1°C
1111 1111
0.25°C
1111 1111
0°C
0000 0000
+0.25°C
0000 0000
+1°C
0000 0001
+4°C
0000 0100
+127.75°C
0111 1111
One-Shot Register
The one-shot register is used to initiate a conversion and com-
parison cycle when the ADT7461 is in standby mode, after
which the device returns to standby. Writing to the one-shot
register address (0×0F) causes the ADT7461 to perform a con-
version and comparison on both the internal and the external
temperature channels. This is not a data register as such, and it
is the write operation to Address 0×0F that causes the one-shot
conversion. The data written to this address is irrelevant and is
not stored.
Consecutive ALERT Register
The value written to this register determines how many out-of-
limit measurements must occur before an ALERT is generated.
The default value is that one out-of-limit measurement gener-
ates an ALERT. The maximum value that can be chosen is 4.
The purpose of this register is to allow the user to perform
some filtering of the output. This is particularly useful at the
fastest three conversion rates, where no averaging takes place.
This register is at Address 0×22.
Table 11. Consecutive ALERT Register Bit
Register Value
Measurements Required
y××× 000×
1
y××× 001×
2
y××× 011×
3
y××× 111×
4
× = Don’t care bit.
y = SMBus timeout bit. Default = 0. See SMBus section for more information.
0×12
00 00 0000
00 00 0000
00 000000
10 00 0000
00 00 0000
01 00 0000
00 00 0000
00 00 0000
11 00 0000
Number of Out-of-Limit
Rev. 0 | Page 13 of 24
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