參數(shù)資料
型號(hào): ADT7516
廠商: Analog Devices, Inc.
元件分類: 溫度/濕度傳感器
英文描述: SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC
中文描述: SPI/I2C兼容,溫度傳感器,四通道ADC和四路電壓輸出DAC
文件頁(yè)數(shù): 23/44頁(yè)
文件大?。?/td> 1350K
代理商: ADT7516
ADT7516/ADT7517/ADT7519
FUNCTIONAL DESCRIPTION—ANALOG INPUTS
Single-Ended Inputs
The ADT7516/ADT7517/ADT7519 offer four single-ended
analog input channels. The analog input range is from 0 V to
2.28 V, or 0 V to V
DD
. To maintain the linearity specification, it is
recommended that the maximum V
DD
value be set at 5 V.
Selection between the two input ranges is done by Bit C4 of the
Control Configuration 3 register (Address 1Ah). Setting this bit
to 0 sets up the analog input ADC reference to be sourced from
the internal voltage reference of 2.28 V. Setting the bit to 1 sets
up the ADC reference to be sourced from V
DD
.
Rev. A | Page 23 of 44
The ADC resolution is 10 bits and is mostly suitable for dc input
signals. Bits C1:2 of the Control Configuration 1 register
(Address 18h) are used to set up Pins 7 and 8 as AIN1 and
AIN2. Figure 48 shows the overall view of the 4-channel analog
input path.
M
U
L
T
I
P
L
E
X
E
R
10-BIT
ADC
TO ADC
VALUE
REGISTER
AIN1
AIN2
AIN3
AIN4
0
Figure 48. Quad Analog Input Path
Converter Operation
The analog input channels use a successive approximation ADC
based on a capacitor DAC. Figure 49 and Figure 50 show sim-
plified schematics of the ADC. Figure 49 shows the ADC during
acquisition phase. SW2 is closed and SW1 is in Position A. The
comparator is held in a balanced condition and the sampling
capacitor acquires the signal on AIN.
CONTROL
LOGIC
CAP DAC
ACQUISITION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
AIN
SW1
A
B
SW2
REF/2
0
Figure 49. ADC Acquisition Phase
CONTROL
LOGIC
CAP DAC
CONVERSION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
AIN
SW1
A
B
SW2
REF/2
0
Figure 50. ADC Conversion Phase
When the ADC eventually goes into conversion phase (see
Figure 50), SW2 opens and SW1 moves to position B, causing
the comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 51 shows the ADC transfer function for the
analog inputs.
ADC TRANSFER FUNCTION
The output coding of the ADT7516/ADT7517/ADT7519 analog
inputs is straight binary. The designed code transitions occur
midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSB). The LSB is V
DD
/1024 or internal V
REF
/1024, internal
V
REF
= 2.28 V. The ideal transfer characteristic is shown in
Figure 51.
111...111
111...110
111...000
011...111
+V
REF
– 1LSB
ANALOG INPUT
0V 1/2LSB
A
1LSB = INT V
REF
/1024
1LSB = V
DD
/1024
000...010
000...001
0
Figure 51. Single-Ended Transfer Function
To work out the voltage on any analog input channel, the
following method can be used:
1 LSB =
reference
(v)/1024
Convert value read back from AIN value register into decimal.
( )
value
AIN
voltage
AIN
×
=
size
LSB
d
= decimal
Example:
Internal reference used. Therefore V
REF
= 2.28 V.
AIN value = 512d
3
10
226
.
1024
/
28
.
=
1
×
=
V
size
LSB
V
voltage
AIN
14
.
10
226
.
×
512
3
=
×
=
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