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ADT7518
Rev. A | Page 26 of 40
UNLOCK ASSOCIATED
MSB REGISTERS
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
0
Figure 52. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked, leaving the user with the option of just reading back
8 bits (MSB) of a 10-bit conversion result. Reading an MSB
register first does not lock other MSB registers, and likewise
reading an LSB register first does not lock other LSB registers.
Table 10. ADT7518 Registers
RD/WR
Address
Name
00h
Interrupt Status 1
01h
Interrupt Status 2
02h
Reserved
03h
Internal Temp and V
DD
LSBs
04h
External Temp and AIN1 to AIN4 LSBs
05h
Reserved
06h
V
DD
MSBs
07h
Internal Temp MSBs
08h
External Temp MSBs/AIN1 MSBs
09h
AIN2 MSBs
0Ah
AIN3 MSBs
0Bh
AIN4 MSBs
0Ch–10h
Reserved
11h
DAC A MSBs
12h
Reserved
13h
DAC B MSBs
14h
Reserved
15h
DAC C MSBs
16h
Reserved
17h
DAC D MSBs
18h
Control Configuration 1
19h
Control Configuration 2
1Ah
Control Configuration 3
1Bh
DAC Configuration
1Ch
LDAC Configuration
1Dh
Interrupt Mask 1
1Eh
Interrupt Mask 2
1Fh
Internal Temp Offset
20h
External Temp Offset
21h
Internal Analog Temp Offset
22h
External Analog Temp Offset
23h
V
DD
V
HIGH
Limit
24h
V
DD
V
LOW
Limit
25h
Internal T
HIGH
Limit
26h
Internal T
LOW
Limit
27h
External T
HIGH
/AIN1 V
HIGH
Limits
28h
External T
LOW
/AIN1 V
LOW
Limits
29h–2Ah
Reserved
2Bh
AIN2 V
HIGH
Limit
2Bh
AIN2 V
HIGH
Limit
2Ch
AIN2 V
LOW
Limit
2Dh
AIN3 V
HIGH
Limit
2Eh
AIN3 V
LOW
Limit
Power-On
Default
00h
00h
00h
00h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
D8h
D8h
C7h
62h
64h
C9h
FFh
00h
FFh
FFh
00h
FFh
00h
RD/WR
Address
2Fh
30h
31h–4Ch
4Dh
Name
AIN4 V
HIGH
Limit
AIN4 V
LOW
Limit
Reserved
Device ID
Power-On
Default
FFh
00h
03h/0Bh/
07h
41h
04h
00h
00h
00h
4Eh
4Fh
50h–7Eh
7Fh
80h–FFh
Interrupt Status 1 Register (Read-Only) [Address = 00h]
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
Table 11. Interrupt Status 1 Register
D7
D6
D5
D4
0*
0*
0*
0*
Manufacturer’s ID
Silicon Revision
Reserved
SPI Lock Status
Reserved
D3
0*
D2
0*
D1
0*
D0
0*
*
Default settings at power-up
Table 12.
Bit
Function
D0
1 when the internal temperature value exceeds T
HIGH
limit. Any
internal temperature reading greater than the set limit will
cause an out-of-limit event.
D1
1 when internal temperature value exceeds T
LOW
limit. Any
internal temperature reading less than or equal to the set limit
will cause an out-of-limit event.
D2
This status bit is linked to the configuration of Pins 7 and 8. If
configured for the external temperature sensor, this bit is 1
when the external temperature value the exceeds T
HIGH
limit.
The default value for this limit register is –1°C, so any external
temperature reading greater than the set limit will cause an
out-of-limit event. If configured for AIN1 and AIN2, this bit is 1
when AIN1 input voltage exceeds V
HIGH
or V
LOW
limits.
D3
1 when external temperature value exceeds T
LOW
limit. The
default value for this limit register is 0°C, so any external
temperature reading less than or equal to the set limit will
cause an out-of-limit event.
D4
1 Indicates a fault (open or short) for the external temperature
sensor.
D5
1 when AIN2 voltage is greater than its corresponding V
HIGH
limit. 1 when AIN2 voltage is less than or equal to its
corresponding V
LOW
limit.
D6
1 when AIN3 voltage is greater than its corresponding V
HIGH
limit. 1 when AIN3 voltage is less than or equal to its
corresponding V
LOW
limit.
D7
1 when AIN4 voltage is greater than its corresponding V
HIGH
limit. 1 when AIN4 voltage is less than or equal to its
corresponding V
LOW
limit.
Interrupt Status 2 Register (Read-Only) [Address = 01h]
This 8-bit read-only register reflects the status of the V
DD
inter-
rupt that can cause the INT/INT pin to go active. This register is
reset by a read operation, provided that any out-of-limit event
has been corrected. It is also reset by a software reset.