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| 型號： | ADT7518ARQZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DAC |
| 中文描述： | DIGITAL TEMP SENSOR-SERIAL, 10BIT(s), 5Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | LEAD FREE, MO-137-AB, QSOP-16 |
| 文件頁數(shù)： | 31/40頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ADT7518ARQZ-REEL7 |
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ADT7518
Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]
This mask register is an 8-bit read/write register that can be
used to mask any interrupts that can cause the INT/INT pin to
go active.
Rev. A | Page 31 of 40
Table 41. Interrupt Mask 2
D7
D6
D7
D6
0*
0*
*
Default settings at power-up
Table 42.
Bit
D0:D3
D4
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
Function
Reserved. Write 0s only.
0 = Enable V
DD
interrupts.
1 = Disable V
DD
interrupts.
Reserved. Write 0s only.
D5:D7
Internal Temperature Offset Register (Read/Write)
[Address = 1Fh]
This register contains the offset value for the internal temp-
erature channel. A twos complement number can be written to
this register which is then added to the measured result before it
is stored or compared to limits. In this way, a one-point cali-
bration can be done whereby the whole transfer function of the
channel can be moved up or down. From a software point of
view, this may be a very simple method to vary the charac-
teristics of the measurement channel if the thermal charac-
teristics change. Because it is an 8-bit register, the temperature
resolution is 1°C.
Table 43. Internal Temperature Offset
D7
D6
D5
D4
D7
D6
D5
D4
0*
0*
0*
0*
*
Default settings at power-up
External Temperature Offset Register (Read/Write)
[Address = 20h]
This register contains the offset value for the external temp-
erature channel. A twos complement number can be written to
this register, which is then added to the measured result before
it is stored or compared to limits. In this way, a one-point cali-
bration can be done whereby the whole transfer function of the
channel can be moved up or down. From a software point of
view, this may be a very simple method to vary the charac-
teristics of the measurement channel if the thermal charac-
teristics change. Because it is an 8-bit register, the temperature
resolution is 1°C.
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
Table 44. External Temperature Offset
D7
D6
D5
D7
D6
D5
0*
0*
0*
*
Default settings at power-up
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
Internal Analog Temperature Offset Register (Read/Write)
[Address = 21h]
This register contains the offset value for the internal thermal
voltage output. A twos complement number can be written to
this register, which is then added to the measured result before
it is converted by DAC A. Varying the value in this register has
the effect of varying the temperature span. For example, the
output voltage can represent a temperature span of –128°C to
+127°C or even 0°C to +127°C. In essence, this register changes
the position of 0 V on the temperature scale. Temperatures
other than –128°C to +127°C will produce an upper deadband
on the DAC A output. Because it is an 8-bit register, the
temperature resolution is 1°C. The default value is –40°C.
Table 45. Internal Analog Temperature Offset
D7
D6
D5
D7
D6
D5
1*
1*
0*
*
Default settings at power-up
External Analog Temperature Offset Register (Read/Write)
[Address = 22h]
This register contains the offset value for the external thermal
voltage output. A twos complement number can be written to
this register which is then added to the measured result before it
is converted by DAC B. Varying the value in this register has the
effect of varying the temperature span. For example, the output
voltage can represent a temperature span of –128°C to +127°C
or even 0°C to +127°C. In essence, this register changes the
position of 0 V on the temperature scale. Temperatures other
than –128°C to +127°C will produce an upper deadband on the
DAC B output. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is –40°C.
Table 46. External Analog Temperature Offset
D7
D6
D5
D4
D7
D6
D5
D4
1*
1*
0*
1*
D4
D4
1*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
0*
*
Default settings at power-up
V
DD
V
HIGH
Limit Register (Read/Write) [Address = 23h]
This limit register is an 8-bit read/write register that stores the
V
DD
upper limit, which will cause an interrupt and activate the
INT/INT output (if enabled). For this to happen, the measured
V
DD
value has to be greater than the value in this register. The
default value is 5.46 V.
Table 47. V
DD
V
HIGH
Limit
D7
D6
D5
D4
D7
D6
D5
D4
1*
1*
0*
0*
*
Default settings at power-up
D3
D3
0*
D2
D2
1*
D1
D1
1*
D0
D0
1*
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