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| 型號： | ADUC7020BCP62 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 57/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC7020BCP62 |
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Preliminary Technical Data
ADuC702x Series
Rev. PrB | Page 57 of 80
SERIAL PERIPHERAL INTERFACE
The ADuC702x integrates a complete hardware Serial
Peripheral Interface (SPI) on-chip. SPI is an industry standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full
duplex up to a maximum bit rate of 5.6Mbs. The SPI Port can
be configured for Master or Slave operation and typically
consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output
line in master mode and an input line in slave mode.
The MOSI line on the master (data out) should be connected to
the MOSI line in the slave device (data in). The data is
transferred as byte wide (8-bit) serial data, MSB first.
SCL (Serial Clock I/O Pin)
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
In master mode polarity and phase of the clock are controlled
by the SPICON register, and the bit-rate is defined in the
SPIDIV register as follow:
)
1
2
SPIDIV
f
f
coreclock
+
k
serialcloc
×
=
The maximum serial bit clock frequency is 1/8 of the core clock
which, based on a maximum core clock frequency of 45MHz is
just above 5.6Mbs.
In slave mode the SPICON register must be configured with the
phase and polarity of the expected input clock.
In both master and slave modes, the data is transmitted on one
edge of the SCL signal and sampled on the other. It is important
therefore that the polarity and phase are configured the same
for the master and slave devices.
Chip Select (CS) Input Pin
In SPI Slave Mode, a transfer is initiated by the assertion of CS
which is an active low input signal. The SPI port will then
transmit and receive 8-bit data until the transfer is concluded by
desassertion of CS . In slave mode CS is always an input.
SPI registers definition
The following MMR registers are used to control the SPI
interface:
-
SPICON:
16-bit control register
-
SPISTA:
8-bit read only status register
-
SPIDIV:
8-bit serial clock divider register
-
SPITX:
8-bit write only transmit register
-
SPIRX:
8-bit read only receive register
Table 46: SPICON MMR Bit Descriptions
Bit
15-13
12
Description
Reserved
Continuous transfer enable
Set
by user to enable continuous transfer.
In master mode the transfer will continue until no valid data is available in the TX register. CS will be asserted and remain
asserted for the duration of each 8-bit serial transfer until TX is empty
Cleared
by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in
the SPITX register then a new transfer is initiated after a stall period
Loop back enable
Set
by user to connect MISO to MOSI and test software
Cleared
by user to be in normal mode
Slave output enable
Set
by user to enable the slave output
Cleared
by user to disable slave output
Slave select input enable
Set
by user in master mode to enable the output
SPIRX overflow overwrite enable
Set by user, the valid data in the RX register is overwritten by the new serial byte received
11
10
9
8
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