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參數(shù)資料
| 型號： | ADUC7021BCP32 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 40/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC7021BCP32 |
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ADuC702x Series
Preliminary Technical Data
Rev. PrB | Page 40 of 80
10
11
Comparator output configuration bits:
00
Start ADC conversion
01
Reserved
10
Output on CMP
OUT
11
IRQ
Comparator output logic state bit
When low the comparator output is high when the positive input (CMP0) is above the negative input
(CMP1).
When high, the comparator output is high when the positive input is below the negative input
Response time
00
10
μ
s
01
5
μ
s
10
1
μ
s
11
0.5
μ
s
Comparator hysteresis bit:
Set
by user to have an hysteresis of about 7.5mV
Cleared
by user to have no hysteresis
Comparator output rising edge interrupt
Set
automatically when a rising edge occurs on the monitored voltage (CMP0)
Cleared
by user by writing a 1 to this bit.
Comparator output falling edge interrupt
Set
automatically when a falling edge occurs on the monitored voltage (CMP0)
Cleared
by user
DAC0
Reserved
7-6
CMPOC
5
CMPOL
4-3
CMPRES
2
CMPHYST
1
CMPORI
0
CMPOFI
OSCILLATOR AND PLL - POWER CONTROL
The ADuC702x integrates a 32.768kHz oscillator, a clock
divider and a PLL. The PLL locks onto a multiple (1376) of the
internal oscillator to provide a stable 45MHz clock for the
system. The core can operate at this frequency, or at binary
submultiples of it, to allow power saving. The default core clock
is the PLL clock divided by 8 (CD = 3) or 5.6 MHz. The core
clock frequency can be output on the ECLK pin as described
Figure 20. A power down mode is available on the ADuC702x.
The operating mode, clocking mode and programmable clock
divider are controlled via two MMRs, PLLCON and POWCON.
PLLCON controls operating mode of the clock system while
POWCON controls the core clock frequency and the power-
down mode.
PLL
XCLKO
XCLKI
P0.7/ECLK
/2
CD
XCLK
WAKEUP
TIMER
WATCHDOG
TIMER
INT. 32kHz *
OSCILLATOR
CRYSTAL
OSCILLATOR
PERIPHERALS
CORE
SCLKS
MDCLK
MDCLK
AT
POWER
UP
CD
45MHz
32.768kHz
* 32.768kHz +/-3%
Figure 20: clocking system
A certain sequence has to be followed to write in the PLLCON
and POWCON registers, to prevent accidental programming.
PLLCON:
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
POWCON:
POWKEY1 = 0x01
POWCON = 0x00
POWKEY1 = 0xF4
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