參數(shù)資料
型號： ADUC7022BCPZ62-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 75/104頁
文件大?。?/td> 0K
描述： IC MSU 12BIT 1MSPS UART 40-LFCSP
標(biāo)準(zhǔn)包裝： 750
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 72 of 104
Table 99. COMDIV1 Register
Name
Address
Default Value
Access
COMDIV1
0xFFFF0704
0x00
R/W
COMDIV1 is a divisor latch (high byte) register.
Table 100. COMIID0 Register
Name
Address
Default Value
Access
COMIID0
0xFFFF0708
0x01
R
COMIID0 is the interrupt identification register.
Table 101. COMIID0 MMR Bit Descriptions
Bit 2:1
Status Bits
Bit 0
NINT
Priority
Definition
Clearing
Operation
00
1
N/A
No interrupt
N/A
11
0
1 (Highest)
Receive line
status
interrupt
Read
COMSTA0
10
0
2
Receive
buffer full
interrupt
Read
COMRX
01
0
3
Transmit
buffer
empty
interrupt
Write data to
COMTX or
read
COMIID0
00
0
4 (Lowest)
Modem
status
interrupt
Read
COMSTA1
Table 102. COMCON0 Register
Name
Address
Default Value
Access
COMCON0
0xFFFF070C
0x00
R/W
COMCON0 is the line control register.
Table 103. COMCON0 MMR Bit Descriptions
Bit
Name
Description
7
DLAB
Divisor latch access. Set by user to enable access
to the COMDIV0 and COMDIV1 registers. Cleared
by user to disable access to COMDIV0 and
COMDIV1 and enable access to COMRX and
COMTX.
6
BRK
Set break. Set by user to force SOUT to 0. Cleared
to operate in normal mode.
5
SP
Stick parity. Set by user to force parity to defined
values: 1 if EPS = 1 and PEN = 1,
0 if EPS = 0 and PEN = 1.
4
EPS
Even parity select bit. Set for even parity. Cleared
for odd parity.
3
PEN
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no parity
transmission or checking.
2
STOP
Stop bit. Set by user to transmit 1.5 stop bits if the
word length is five bits or 2 stop bits if the word
length is six bits, seven bits, or eight bits. The
receiver checks the first stop bit only, regardless
of the number of stop bits selected. Cleared by user
to generate 1 stop bit in the transmitted data.
1:0
WLS
Word length select:
00 = five bits, 01 = six bits, 10 = seven bits,
11 = eight bits.
Table 104. COMCON1 Register
Name
Address
Default Value
Access
COMCON1
0xFFFF0710
0x00
R/W
COMCON1 is the modem control register.
Table 105. COMCON1 MMR Bit Descriptions
Bit
Name
Description
7:5
Reserved.
4
LOOPBACK
Loopback. Set by user to enable loopback
mode. In loopback mode, SOUT (see Table 78)
is forced high. The modem signals are also
directly connected to the status inputs (RTS
to CTS and DTR to DSR). Cleared by user to
be in normal mode.
3
PEN
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no
parity transmission or checking.
2
STOP
Stop bit. Set by user to transmit 1.5 stop bits
if the word length is five bits, or 2 stop bits if
the word length is six bits, seven bits, or
eight bits. The receiver checks the first stop
bit only, regardless of the number of stop bits
selected. Cleared by user to generate 1 stop
bit in the transmitted data.
1
RTS
Request to send. Set by user to force the RTS
output to 0. Cleared by user to force the RTS
output to 1.
0
DTR
Data terminal ready. Set by user to force the
DTR output to 0. Cleared by user to force the
DTR output to 1.
Table 106. COMSTA0 Register
Name
Address
Default Value
Access
COMSTA0
0xFFFF0714
0x60
R
COMSTA0 is the line status register.
Table 107. COMSTA0 MMR Bit Descriptions
Bit
Name
Description
7
Reserved.
6
TEMT
COMTX and shift register empty status bit. Set
automatically if COMTX and shift register are
empty. Cleared automatically when writing to
COMTX.
5
THRE
COMTX empty. Set automatically if COMTX is
empty. Cleared automatically when writing to
COMTX.
4
BI
Break error. Set when SIN is held low for more than
the maximum word length. Cleared automatically.
3
FE
Framing error. Set when an invalid stop bit occurs.
Cleared automatically.
2
PE
Parity error. Set when a parity error occurs.
Cleared automatically.
1
OE
Overrun error. Set automatically if data is over-
written before being read. Cleared automatically.
0
DR
Data ready. Set automatically when COMRX is full.
Cleared by reading COMRX.
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