參數(shù)資料
型號： ADUC7027BSTZ62I
廠商： Analog Devices Inc
文件頁數(shù)： 87/104頁
文件大小： 0K
描述： IC MCU FLASH 62K ANLG I2C 80LQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 90
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 托盤
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 83 of 104
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 23 interrupt sources on the ADuC7019/20/21/22/
24/25/26/27/28/29 that are controlled by the interrupt
controller. Most interrupts are generated from the on-chip
peripherals, such as ADC and UART. Four additional interrupt
sources are generated from external interrupt request pins,
IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI CPU core only
recognizes interrupts as one of two types: a normal interrupt
request IRQ or a fast interrupt request FIQ. All the interrupts
can be masked separately.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register (except for Bit 23) represent
the same interrupt source as described in Table 160.
Table 160. IRQ/FIQ MMRs Bit Description
Bit
Description
0
All interrupts OR’ed (FIQ only)
1
SWI
2
Timer0
3
Timer1
4
Wake-up timer (Timer2)
5
Watchdog timer (Timer3)
6
Flash control
7
ADC channel
8
PLL lock
9
I2C0 slave
10
I2C0 master
11
I2C1 master
12
SPI slave
13
SPI master
14
UART
15
External IRQ0
16
Comparator
17
PSM
18
External IRQ1
19
PLA IRQ0
20
PLA IRQ1
21
External IRQ2
22
External IRQ3
23
PWM trip (IRQ only)/PWM sync (FIQ only)
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
Table 161. IRQSTA Register
Name
Address
Default Value
Access
IRQSTA
0xFFFF0000
0x00000000
R
IRQSTA (read-only register) provides the current-enabled IRQ
source status. When set to 1, that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
Table 162. IRQSIG Register
Name
Address
Default Value
Access
IRQSIG
0xFFFF0004
0x00XXX0001
R
1
X indicates an undefined value.
IRQSIG reflects the status of the different IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the IRQSIG
is set; otherwise, it is cleared. The IRQSIG bits are cleared when
the interrupt in the particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR. IRQSIG is read only.
Table 163. IRQEN Register
Name
Address
Default Value
Access
IRQEN
0xFFFF0008
0x00000000
R/W
IRQEN provides the value of the current enable mask. When
each bit is set to 1, the source request is enabled to create an
IRQ exception. When each bit is set to 0, the source request is
disabled or masked, which does not create an IRQ exception.
Note that to clear an already enabled interrupt source, the user
must set the appropriate bit in the IRQCLR register. Clearing an
interrupt’s IRQEN bit does not disable the interrupt.
Table 164. IRQCLR Register
Name
Address
Default Value
Access
IRQCLR
0xFFFF000C
0x00000000
W
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
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