- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11791 > ADUC7129BSTZ126-RL (Analog Devices Inc)IC DAS MCU ARM7 ADC/DDS 80-LQFP PDF資料下載
參數(shù)資料
| 型號： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Rev. 0 | Page 67 of 92
I2CxSRX Register
Name
Address
Default Value
Access
I2C0SRX
0xFFFF0808
0x00
R
I2C1SRX
0xFFFF0908
0x00
R
I2CxSRX is a receive register for the slave channel.
I2CxSTX Register
Name
Address
Default Value
Access
I2C0STX
0xFFFF080C
0x00
W
I2C1STX
0xFFFF090C
0x00
W
I2CxSTX is a transmit register for the slave channel.
I2CxMRX Register
Name
Address
Default Value
Access
I2C0MRX
0xFFFF0810
0x00
R
I2C1MRX
0xFFFF0910
0x00
R
I2CxMRX is a receive register for the master channel.
I2CxMTX Register
Name
Address
Default Value
Access
I2C0MTX
0xFFFF0814
0x00
W
I2C1MTX
0xFFFF0914
0x00
W
I2CxMTX is a transmit register for the master channel.
I2CxCNT Register
Name
Address
Default Value
Access
I2C0CNT
0xFFFF0818
0x00
R/W
I2C1CNT
0xFFFF0918
0x00
R/W
I2CxCNT is a master receive data count register. If a master read
transfer sequence is initiated, the I2CxCNT register denotes the
number of bytes (1) to be read from the slave device. By default
this counter is 0, which corresponds to the expected one byte.
I2CxADR Register
Name
Address
Default Value
Access
I2C0ADR
0xFFFF081C
0x00
R/W
I2C1ADR
0xFFFF091C
0x00
R/W
I2CxADR is a master address byte register. The I2CxADR value
is the device address that the master wants to communicate
with. It is automatically transmitted at the start of a master
transfer sequence if there is no valid data in the I2CxMTX
register when the master enable bit is set.
I2CxBYT Register
Name
Address
Default Value
Access
I2C0BYT
0xFFFF0824
0x00
R/W
I2C1BYT
0xFFFF0924
0x00
R/W
I2CxBYT is a broadcast byte register.
I2CxALT Register
Name
Address
Default Value
Access
I2C0ALT
0xFFFF0828
0x00
R/W
I2C1ALT
0xFFFF0928
0x00
R/W
I2CxALT is a hardware general call ID register used in slave mode.
I2CxCFG Register
Name
Address
Default Value
Access
I2C0CFG
0xFFFF082C
0x00
R/W
I2C1CFG
0xFFFF092C
0x00
R/W
I2CxCFG is a configuration register.
Table 94. I2C0CFG MMR Bit Designations
Bit
Description
31:15
Reserved. These bits should be written by the user as 0.
14
Enable Stop Interrupt.
Set by user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition and matching
address.
Cleared by user to disable the generation of an interrupt upon receiving a stop condition.
13
Reserved. This bit should be written by the user as 0.
12
Reserved. This bit should be written by the user as 0.
11
Enable Stretch SCL. Holds SCL low.
Set by user to stretch the SCL line.
Cleared by user to disable stretching of the SCL line.
10
Reserved. This bit should be written by the user as 0.
9
Slave Tx FIFO Request Interrupt Enable.
Cleared by user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to
input data into the slave Tx FIFO if it is empty. At 400 kSPS, and with the core clock running at 41.78 MHz, the user has 45 clock
cycles to take appropriate action, taking interrupt latency into account.
Set by user to disable the slave Tx FIFO request interrupt.
8
General Call Status Bit Clear.
Set by user to clear the general call status bits.
Cleared automatically by hardware after the general call status bits have been cleared.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| D38999/20FC8SC | CONN RCPT 8POS WALL MNT W/SCKT |
| D38999/26WC8PB | CONN PLUG 8POS STRAIGHT W/PINS |
| MS27473E18A11P | CONN PLUG 11POS STRAIGHT W/PINS |
| AT32UC3C2512C-Z2ZR | IC MCU AVR32 512K FLASH 64QFN |
| MS27484E10B98P | CONN PLUG 6POS STRAIGHT W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC7129BSTZ126-RL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| aduc7229bcpz126 | 制造商:Analog Devices 功能描述: |
| ADUC7229BCPZ126-RL | 制造商:Analog Devices 功能描述: |
| ADUC812 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter⑩, Multichannel 12-Bit ADC with Embedded FLASH MCU |
| ADUC812_03 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。