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REV. PrB
–5–
ADuC842
N O T E S
1
T emperature Range -40oC to +85oC .
2
AD C L inearity is guaranteed during normal MicroC onverter C ore operation.
3
ADC L SB Size = Vref / 2^12 i.e for Internal Vref=2.5V, 1L SB = 610uV and for External Vref =1V, 1L SB = 244uV.
4
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
5
Based on external AD C system components the user may need to execute a system calibration to remove additional external channel errors
and achieve these specifications.
6
SNR calculation includes distortion and noise components.
7
C hannel to C hannel C rosstalk is measured on adjacent channels.
8
T he T emperature Monitor will give a measure of the die temperature directly, air temperature can be inferred from this result.
9
T hese numbers are not production tested but are guaranteed by D esign and/or C haracterization data on production release.
10
DAC linearity is calculated using :
reduced code range of 48 to 4095, 0 to Vref range.
reduced code range of 48 to 3945, 0 to V
range.
DAC Output Load = 10K Ohms and 100 pF.
11
DAC Differential NonL inearity specified on 0 to Vref and 0 to Vdd ranges
12
DAC specification for output impedance in the unbuffered case depends on DAC code
13
D AC specifications for Isink, voltage output settling time and digital-to-analog glitch engergy depend on external buffer implementation in
unbuffered mode.
14
Measured with Vref and C ref pins decoupled with 0.1μF capacitors to graound. Power-up time for the Internal Reference will be determined
by the value of the decoupling capacitor chosen for both the Vref and Cref pins.
15
When using an External Reference device, the internal bandgap reference input can be bypassed by setting the ADC C ON1.6 bit. In this
mode the Vref and C ref pins need to be shorted together for correct operation.
16
F lash/EE Memory Reliability C haracteristics apply to both the F lash/EE program memory and the F lash/EE data memory.
17
Endurance is qualified to 100 K cycles as per JEDEC Std. 22 method A117 and measured at -40oC , +25oC , and +85oC , typical endurance at
25oC is 700 K cycles.
18
Retention lifetime equivalent at junction temperature (T j) = 55oC as per JED EC Std. 22 method A117. Retention lifetime based on an
activation energy of 0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this
data sheet.
19
Power Supply current consumption is measured in Normal, Idle, and Power-D own Modes under the following conditions:
Normal M ode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal
software loop.
Idle Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0=1, C ore
Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed
via C D bits in PL L C ON, PC ON.0=1, C ore Execution suspended inpower-down mode, OSC turned ON or OFF via
OSC _PD bit (PL L C ON.7) in PL L C ON SF R
20
D
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program
or erase cycle.
Specifications subject to change without notice.