參數(shù)資料
型號: ADUC842BSZ62-5
廠商: Analog Devices Inc
文件頁數(shù): 8/88頁
文件大?。?/td> 0K
描述: IC ADC/DAC 12BIT W/MCU 52-MQFP
標準包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: DMA,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 52-QFP
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 16 of 88
FUNCTIONAL DESCRIPTION
8052 INSTRUCTION SET
Table 4 documents the number of clock cycles required for each
instruction. Most instructions are executed in one or two clock
cycles, resulting in a 16 MIPS peak performance when operating
at PLLCON = 00H on the ADuC842/ADuC843. On the ADuC841,
20 MIPS peak performance is possible with a 20 MHz external
crystal.
Table 4. Instructions
Mnemonic
Description
Bytes
Cycles
Arithmetic
ADD A,Rn
Add register to A
1
ADD A,@Ri
Add indirect memory to A
1
2
ADD A,dir
Add direct byte to A
2
ADD A,#data
Add immediate to A
2
ADDC A,Rn
Add register to A with carry
1
ADDC A,@Ri
Add indirect memory to A with carry
1
2
ADDC A,dir
Add direct byte to A with carry
2
ADD A,#data
Add immediate to A with carry
2
SUBB A,Rn
Subtract register from A with borrow
1
SUBB A,@Ri
Subtract indirect memory from A with borrow
1
2
SUBB A,dir
Subtract direct from A with borrow
2
SUBB A,#data
Subtract immediate from A with borrow
2
INC A
Increment A
1
INC Rn
Increment register
1
INC @Ri
Increment indirect memory
1
2
INC dir
Increment direct byte
2
INC DPTR
Increment data pointer
1
3
DEC A
Decrement A
1
DEC Rn
Decrement register
1
DEC @Ri
Decrement indirect memory
1
2
DEC dir
Decrement direct byte
2
MUL AB
Multiply A by B
1
9
DIV AB
Divide A by B
1
9
DA A
Decimal adjust A
1
2
Logic
ANL A,Rn
AND register to A
1
ANL A,@Ri
AND indirect memory to A
1
2
ANL A,dir
AND direct byte to A
2
ANL A,#data
AND immediate to A
2
ANL dir,A
AND A to direct byte
2
ANL dir,#data
AND immediate data to direct byte
3
ORL A,Rn
OR register to A
1
ORL A,@Ri
OR indirect memory to A
1
2
ORL A,dir
OR direct byte to A
2
ORL A,#data
OR immediate to A
2
ORL dir,A
OR A to direct byte
2
ORL dir,#data
OR immediate data to direct byte
3
XRL A,Rn
Exclusive-OR register to A
1
XRL A,@Ri
Exclusive-OR indirect memory to A
2
XRL A,#data
Exclusive-OR immediate to A
2
XRL dir,A
Exclusive-OR A to direct byte
2
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