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參數(shù)資料
| 型號(hào)： | ADUC843BCPZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/88頁 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 12BIT ADC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 64 of 88
TIMER/COUNTER OPERATING MODES
The following sections describe the operating modes for
Timer/Counter 2. The operating modes are selected by bits in
the T2CON SFR, as shown in Table 31.
Table 31. T2CON Operating Modes
RCLK (or) TCLK
CAP2
TR2
Mode
0
1
16-Bit Autoreload
0
1
16-Bit Capture
1
X
1
Baud Rate
X
0
OFF
16-Bit Autoreload Mode
Autoreload mode has two options that are selected by Bit EXEN2
in T2CON. If EXEN2 = 0, then when Timer 2 rolls over, it not
only sets TF2 but also causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer 2 still
performs the above, but with the added feature that a 1-to-0
transition at external input T2EX will also trigger the 16-bit
reload and set EXF2. Autoreload mode is illustrated in Figure 70.
16-Bit Capture Mode
Capture mode also has two options that are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer
or counter that, upon overflowing, sets Bit TF2, the Timer 2
overflow bit, which can be used to generate an interrupt. If
EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0
transition on external input T2EX causes the current value in
the Timer 2 registers, TL2 and TH2, to be captured into
registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2EX causes Bit EXF2 in T2CON to be set, and
EXF2, like TF2, can generate an interrupt. Capture mode is
illustrated in Figure 71. The baud rate generator mode is
selected by RCLK = 1 and/or TCLK = 1.
In either case, if Timer 2 is being used to generate the baud rate,
the TF2 interrupt flag will not occur. Therefore, Timer 2
interrupts will not occur, so they do not have to be disabled. In
this mode, the EXF2 flag, however, can still cause interrupts,
which can be used as a third external interrupt. Baud rate
generation is described as part of the UART serial port
operation in the following section.
CORE
CLK*
T2
PIN
C/T2 = 0
C/T2 = 1
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
TF2
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L
RCAP2H
* CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
03260-
0-
069
Figure 70. Timer/Counter 2, 16-Bit Autoreload Mode
TF2
CORE
CLK
*
T2
PIN
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
CAPTURE
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L
RCAP2H
C/ T2 = 0
C/ T2 = 1
* CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
03260-
0-
070
Figure 71. Timer/Counter 2, 16-Bit Capture Mode
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