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參數(shù)資料
| 型號： | ADUC843BSZ62-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/88頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 52-MQFP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 8.38MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 10 of 88
Mnemonic
Type
Function
P3.0–P3.7
I/O
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high
by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low source current because of the internal pull-up resistors. Port 3 pins also contain various secondary
functions, which are described below.
PWMC
I
PWM Clock Input.
PWM0
O
PWM0 Voltage Output. PWM outputs can be configured to use Ports 2.6 and 2.7 or Ports 3.4 and 3.3.
PWM1
O
PWM1 Voltage Output. See the CFG841/CFG842 register for further information.
RxD
I/O
Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of the Serial (UART) Port.
TxD
O
Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of the Serial (UART) Port.
INT0
I
Interrupt 0. Programmable edge or level triggered interrupt input; can be programmed to one of two priority
levels. This pin can also be used as a gate control input to Timer 0.
INT1
I
Interrupt 1. Programmable edge or level triggered interrupt input; can be programmed to one of two priority
levels. This pin can also be used as a gate control input to Timer 1.
T0
I
Timer/Counter 0 Input.
T1
I
Timer/Counter 1 Input.
CONVST
I
Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled. A
low-to-high transition on this input puts the track-and-hold into hold mode and starts the conversion.
EXTCLK
I
Input for External Clock Signal. Has to be enabled via the CFG842 register.
WR
O
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD
O
Read Control Signal, Logic Output. Enables the external data memory to Port 0.
XTAL2
O
Output of the Inverting Oscillator Amplifier.
XTAL1
I
Input to the Inverting Oscillator Amplifier.
DGND
G
Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7
(A8–A15)
(A16–A23)
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high
by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low source current because of the internal pull-up resistors. Port 2 emits the middle and high-order
address bytes during accesses to the external 24-bit external data memory space.
PSEN
O
Program Store Enable, Logic Output. This pin remains low during internal program execution. PSEN is used to
enable serial download mode when pulled low through a resistor on power-up or reset. On reset this pin will
momentarily become an input and the status of the pin is sampled. If there is no pulldown resistor in place the pin
will go momentarilly high and then user code will execute. If a pull-down resistor is in place, the embedded serial
download/debug kernel will execute.
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte and page byte for 24-bit address
space accesses of the address into external data memory.
EA
I
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal
program memory locations. The parts do not support external code memory. This pin should not be left floating.
P0.7–P0.0
(A0-A7)
I/O
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state
can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during
accesses to external data memory. In this application, it uses strong internal pull-ups when emitting 1s.
Types: P = Power, G = Ground, I= Input, O = Output., NC = No Connect
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC843BSZ62-5 | 功能描述:IC ADC 12BIT W/FLASH MCU 52-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設備:電容感應，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤 |
| ADUC844 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC844BCP32-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC844BCP32-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC844BCP62-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU |
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