I2C SERIAL INTERFACE " />
參數(shù)資料
型號(hào)： ADUC848BSZ8-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 67/108頁(yè)
文件大小： 0K
描述： IC MCU FLASH W/16BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 96
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 61 of 108
I2C SERIAL INTERFACE
The ADuC845/ADuC847/ADuC848 support a fully licensed
I2C serial interface. The I2C interface is implemented as a full
hardware slave and software master. SDATA (Pin 27 on the
MQFP package and Pin 29 on the LFCSP package) is the data
I/O pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the
LFCSP package) is the serial interface clock for the SPI interface.
The I2C interface on the parts is fully independent of all other
pin/function multiplexing. The I2C interface incorporated on
the ADuC845/ADuC847/ADuC848 also includes a second
address register (I2CADD1) at SFR Address F2H with a default
power-on value of 7FH. The I2C interface is always available to
the user and is not multiplexed with any other I/O functionality
on the chip. This means that the I2C and SPI interfaces can be
used at the same time.
Note that when using the I2C and SPI interfaces simultaneously,
they both use the same interrupt routine (Vector Address 3BH).
When an interrupt occurs from one of these, it is necessary to
interrogate each interface to see which one has triggered the ISR
request.
The four SFRs that are used to control the I2C interface are
described next.
I2CCON—I2C Control Register
SFR Address:
E8H
Power-On Default:
00H
Bit Addressable:
Yes
Table 40. I2CCON SFR Bit Designations
Bit No.
Name
Description
7
MDO
I2C Software Master Data Output Bit (master mode only).
This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit is output on
the SDATA pin if the data output enable bit (MDE) is set.
6
MDE
I2C Software Output Enable Bit (master mode only).
Set by the user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable the SDATA pin as an input (Rx).
5
MCO
I2C Software Master Clock Output Bit (master mode only).
This bit is used to implement the SCLK for a master I2C transmitter in software. Data written to this bit is output on
the SCLK pin.
4
MDI
I2C Software Master Data Input Bit (master mode only).
This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into
this bit on an SCLK transition if the data output enable (MDE) bit is 0.
3
I2CM
I2C Master/Slave Mode Bit.
Set by the user to enable I2C software master mode.
Cleared by the user to enable I2C hardware slave mode.
2
I2CRS
I2C Reset Bit (slave mode only).
Set by the user to reset the I2C interface.
Cleared by the user code for normal I2C operation.
1
I2CTX
I2C Direction Transfer Bit (slave mode only).
Set by the MicroConverter if the I2C interface is transmitting.
Cleared by the MicroConverter if the I2C interface is receiving.
0
I2CI
I2C Interrupt Bit (slave mode only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared by the MicroConverter when the user code reads the I2CDAT SFR. I2CI should not be cleared by user code.
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