TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTT" />
參數(shù)資料
型號(hào)： ADV3003ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 0K
描述： IC EQUALZR HDMI/DVI TMDS 40LFCSP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： DVI，HDMI 均衡器/驅(qū)動(dòng)器
接口： TMDS
電源電壓： 3 V ~ 3.6 V
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
安裝類型： 表面貼裝
ADV3003
Rev. 0 | Page 3 of 16
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
NRZ
2.25
Gbps
Bit Error Rate (BER)
PRBS 223 1
109
Added Deterministic Jitter
DR ≤ 2.25 Gbps, PRBS 27 1
25
ps (p-p)
Added Random Jitter
1
ps (rms)
Differential Intrapair Skew
At output
1
ps
Differential Interpair Skew1
At output
50
ps
EQUALIZATION PERFORMANCE
Receiver (Fixed Setting)2
Boost frequency = 1.125 GHz
12
dB
Transmitter (Pre-Emphasis On)3
Boost frequency = 1.125 GHz
6
dB
INPUT CHARACTERISTICS
Input Voltage Swing
Differential
150
1200
mV
Input Common-Mode Voltage (VICM)
AVCC 800
AVCC
mV
OUTPUT CHARACTERISTICS4
High Voltage Level
Single-ended high speed channel
AVCC 200
AVCC + 10
mV
Low Voltage Level
Single-ended high speed channel
AVCC 600
AVCC 400
mV
Rise/Fall Time (20% to 80%)
75
178
ps
TERMINATION
Input Termination Resistance
Single-ended
50
Ω
Output Termination Resistance
Single-ended
50
Ω
POWER SUPPLY
AVCC
Operating range (3.3 V ± 10%)
3
3.3
3.6
V
QUIESCENT CURRENT
AVCC
Output disabled
20
40
mA
Output enabled, pre-emphasis off
32
50
mA
Output enabled, pre-emphasis on
66
80
mA
VTTI
Input termination on5
40
54
mA
VTTO
Output termination on, pre-emphasis off
40
50
mA
Output termination on, pre-emphasis on
80
100
mA
Output disabled
0
1
mA
POWER DISSIPATION6
Output disabled
66
148
mW
Output enabled, pre-emphasis off
370
553
mW
Output enabled, pre-emphasis on
686
937
mW
PARALLEL CONTROL INTERFACE
TX_EN, PE_EN
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
1 Differential interpair skew is measured between the TMDS pairs of the HDMI/DVI link.
2 ADV3003 output meets the transmitter eye diagram mask as defined in the HDMI Standard Version 1.3a and the DVI Standard Version 1.0.
3 Cable output meets the receiver eye diagram mask as defined in the HDMI Standard Version 1.3a and the DVI Standard Version 1.0.
4 PE = 0 dB.
5 Typical value assumes the HDMI/DVI link is active with nominal signal swings. Minimum and maximum limits are measured at the extremes of input termination
resistance and input voltage swing, respectively .
6 The total power dissipation excludes power dissipated in the 50 Ω off-chip loads.
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