參數(shù)資料
型號(hào)： ADV7152LS220
廠商： ANALOG DEVICES INC
元件分類(lèi)： 顯示控制器
英文描述： CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
中文描述： PALETTE-DAC DSPL CTLR, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 30/32頁(yè)
文件大?。?/td> 454K
代理商： ADV7152LS220
ADV7152
–30–
REV. B
the graphics pipeline and after a number of clocks get latched
into the DAC T est Register. T his data can then be read from
the Pixel T est Register and the DAC T est Registers over the
MPU Port. T his data will remain in the Pixel T est Registers and
the DAC T est Registers until the next rising edge of R7 causes
new data to be latched in.
In the above example, the next rising edge of R7 occurs on the
Pixel
n
input. T herefore the data in the Pixel T est Registers and
DAC T est Registers must be read over the MPU before the
Pixel
n
data is applied, otherwise they will be overwritten by the
Pixel
n
data and the Pixel 2 data will be lost.
Pixel T est Register
T he read-only Pixel T est Register is 24 bits wide, 8 bits each for
red, green and blue. It is situated directly after the Pixel Mask
Register. After data is latched into this register by a transition on
R7, it is read in three cycles over the MPU Port as described in
the “Microprocessor (MPU) Port” section.
DAC T est Register
T he DAC T est Register is latched with data some CLOCK s
after the Pixel T est Register. T he DAC T est Register is a 30-bit
wide read-only register, corresponding to 10 bits each for red,
green and blue data. It is located the Color Palette RAM. If the
RAM-DAC is in 8-bit after resolution mode, the upper two bits
of the red, green and blue data will be zero. After data is latched
into the DAC T est Register by a transition on R7, it is read
in three or six cycles over the MPU Port as described in the
“Microprocessor (MPU) Port” section.
SYNC
,
BLANK
and I
PLL
T est Register
T his is an 8-bit wide register but with only three effective bits.
T he three lower bits correspond to
SYNC
,
BLANK
and I
PLL
respectively. T he upper bits should be masked in software. T his
register is at the same position in the graphics pipeline as the
DAC T est Register. When pixel data is latched into the DAC
T est Register, the corresponding status of
SYNC
,
BLANK
and
I
PLL
is latched into this register. It is read over the MPU Port as
described in the “Microprocessor (MPU) Port” section.
(Note: If
BLANK
is low, the corresponding pixel data to the
DAC T est Register will be all “0s.”)
T he ADV7152 contains onboard circuitry which enables both
device and system level test diagnostics. T he test circuitry can
be used to test the frame buffer memory as well as the function-
ality of the ADV7152. A number of test registers are integrated
into the part which effectively allow for monitoring of the graph-
ics pipeline. Pixel data is read from the graphics pipeline inde-
pendent of the pixel CLOCK . T he pixel data itself contains the
triggering information that latches data into the test registers.
T his allows for system diagnostics in a continuously clocked
graphics system. T he test register data is then read by the micro-
processor over the MPU.
Access to the test registers is as described in the “Microproces-
sor (MPU) Port” section. T his section also gives the address
decode locations for the various test registers.
T est T rigger (R7)
T he test trigger is decoded from the pixel data stream. Bit R7 of
the RED channel is assigned the task of latching pixel data into
the test registers. A “0” to “1” or a “1” to “0” (as determined
by bit CR20 of Command Register 2) transition on R7, fills the
test register with the corresponding pixel data. T his effectively
means that a sequence of data travels along the graphics pipe-
line, with the test registers taking a sample only when there is a
transition on Bit R7. T he following example shows a sequence
with the ADV7152 preset to sample the graphics pipeline on a
low to high transition of R7.
RED
00000000
0........
1........
0........
. . .
. . .
0........
1........
0........
GREEN
00000000
........
........
........
BLUE
00000000
........
........
........
Pixel 0:
Pixel 1:
Pixel 2:
Pixel 3:
. . . .
. . . .
Pixel n-1:
Pixel n:
Pixel n:
In the above sequence of pixels, there is a rising edge on R7 on
Pixel 2. T he Red, Green and Blue data for Pixel 2, therefore,
gets latched into the Pixel T est Register. Pixel 2 continues down
........
........
........
........
........
........
APPE NDIX 6
T E ST DIAGNOST ICS
INPUT
MUX
PIXEL TEST
REGISTER
COLOR
REGISTERS
DAC TEST
REGISTERS
COLOR
PALETTE
RAM
DACs
TRIGGER
DECODE
PIXEL
DATA
BLANK
SYNC
D9–D0
C0
C1
CE
R/W
TRIGGER
DECODE
GRAPHICS PIPELINE
GRAPHICS PIPELINE
MPU PORT
SYNC BLANK
I
PLL
TEST
REGISTER
Test/Diagnostic Block Diagram
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ADV7152LS85 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
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