參數(shù)資料
型號： ADV7180KCP32Z-RL
廠商： Analog Devices Inc
文件頁數(shù)： 114/116頁
文件大小： 0K
描述： IC VIDEO DECODER 10BIT 32LFCSP
設(shè)計(jì)資源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
標(biāo)準(zhǔn)包裝： 5,000
類型： 視頻解碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
Data Sheet
ADV7180
Rev. I | Page 97 of 116
Main Map
Bit Description
Bits
(Shading Indicates Default State)
Comments
Notes
Subaddress
Register
7
6
5
4
3
2
1
0
0xE4
SD Saturation Cr
SD_SAT_Cr[7:0]; adjusts
the saturation by affecting
gain on the Cr channel
0
Gain on Cr channel = 42 dB
1
0
Gain on Cb channel = 0 dB
1
Gain on Cb channel = +6 dB
0xE5
NTSC V bit
begin
NVBEG[4:0]; number of
lines after lCOUNT rollover
to set V high
0
1
0
1
NTSC default (ITU-R BT.656)
NVBEGSIGN
0
Set to low when manual programming
1
Not suitable for user programming
NVBEGDELE; delay V bit
going high by one line
relative to NVBEG (even
field)
0
No delay
1
Additional delay by one line
NVBEGDELO; delay V bit
going high by one line
relative to NVBEG (odd
field)
0
No delay
1
Additional delay by one line
0xE6
NTSC V bit end
NVEND[4:0]; number of
lines after lCOUNT rollover
to set V low
0
1
0
NTSC default (ITU-R BT.656)
NVENDSIGN
0
Set to low when manual programming
1
Not suitable for user programming
NVENDDELE; delay V bit
going low by one line
relative to NVEND (even
field)
0
No delay
1
Additional delay by one line
NVENDDELO; delay V bit
going low by one line
relative to NVEND (odd
field)
0
No delay
1
Additional delay by one line
0xE7
NTSC F bit
toggle
NFTOG[4:0]; number of
lines after lCOUNT rollover to
toggle F signal
0
1
NTSC default
NFTOGSIGN
0
Set to low when manual programming
1
Not suitable for user programming
NFTOGDELE; delay
F transition by one line
relative to NFTOG (even
field)
0
No delay
1
Additional delay by one line
NFTOGDELO; delay
F transition by one line
relative to NFTOG
(odd field)
0
No delay
1
Additional delay by one line
0xE8
PAL V bit begin
PVBEG[4:0]; number of
lines after lCOUNT rollover
to set V high
0
1
0
1
PAL default (ITU-R BT.656)
PVBEGSIGN
0
Set to low when manual programming
1
Not suitable for user programming
PVBEGDELE; delay V bit
going high by one line
relative to PVBEG (even
field)
0
No delay
1
Additional delay by one line
PVBEGDELO; delay V bit
going high by one line
relative to PVBEG (odd
field)
0
No delay
1
Additional delay by one line
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