參數(shù)資料
型號: ADV7192KST
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
中文描述: COLOR SIGNAL ENCODER, PQFP80
封裝: LQFP-80
文件頁數(shù): 44/69頁
文件大?。?/td> 664K
代理商: ADV7192KST
ADV7192
–44–
REV. 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR07
ZERO MUST BE
WRITTEN TO
THIS BIT
CLKOUT
PIN CONTROL
OCR01
0
1
ENSABLED
DISABLED
OCR06 – OCR04
ONE MUST BE
WRITTEN TO
THESE BITS
OCR03 – OCR02
ZERO MUST BE
WRITTEN TO
THESE BITS
OCR00
ZERO MUST BE
WRITTEN TO
THIS BIT
Figure 94. Output Clock Register
BRIGHTNESS DETECT REGISTER
(Address (SR5–SR0) = 34H)
The Brightness Detect Register is an 8-bit-wide register used only
to read back data in order to monitor the brightness/darkness of
the incoming video data on a
fi
eld-by-
fi
eld basis. The brightness
information is read from the I
2
C and based on this information,
the color controls or the gamma correction controls may be
adjusted.
The luma data is monitored in the active video area only. The
average brightness I
2
C register is updated on the falling edge of
every
VSYNC
signal.
OUTPUT CLOCK REGISTER (OCR 9–0)
(Address (SR4–SR0) = 35H)
The Output Clock Register is an 8-bit-wide register. Figure 93
shows the various operations under the control of this register.
OCR BIT DESCRIPTION
Reserved (OCR00)
A Logic 0 must be written to this bit.
CLKOUT Pin Control (OCR01)
This bit enables the CLKOUT pin when set to 1 and, there-
fore, outputs a 54 MHz clock generated by the internal PLL.
The PLL and 4
×
Oversampling have to be enabled for this con-
trol to take effect, (MR61 = 0; MR16 = 1).
Reserved (OCR02–03)
A Logic 0 must be written to this bit.
Reserved (OCR04–06)
A Logic 1 must be written to these bits.
Reserved (OCR07)
A Logic 0 must be written to this bit.
相關(guān)PDF資料
PDF描述
ADV7192 Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
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參數(shù)描述
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