參數(shù)資料
型號(hào): ADV7343BSTZ
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
中文描述: SERIAL INPUT LOADING, 11-BIT DAC, QFP64
封裝: ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù): 7/88頁
文件大?。?/td> 1053K
代理商: ADV7343BSTZ
ADV7342/ADV7343
DIGITAL TIMING SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V. PV
DD
= 1.71 V to 1.89 V. V
AA
= 2.6 V to 3.465 V. V
DD_IO
= 2.97 V to 3.63 V.
All specifications T
MIN
to T
MAX
(40°C to +85°C), unless otherwise noted.
Rev. 0 | Page 7 of 88
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT
2,
3
Data Setup Time, t
114
Data Hold Time, t
124
Control Setup Time, t
114
Control Hold Time, t
124
Digital Output Access Time, t
134
Digital Output Hold Time, t
144
PIPELINE DELAY
5
SD
1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED
1
Component Outputs (1×)
Component Outputs (8×)
HD
1
Component Outputs (1×)
Component Outputs (4×)
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2
Video data: C[7:0], Y[7:0], and S[7:0].
3
Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
Conditions
1
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
ED oversampling disabled
ED oversampling enabled
HD oversampling disabled
HD oversampling enabled
Min
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
4.0
3.5
Typ
68
67
78
84
41
46
40
44
Max
12
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
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