參數(shù)資料
型號: AEAS-7500
廠商: Avago Technologies Ltd.
英文描述: Ultra-Precision 16 bit Gray Code Absolute Encoder Module
中文描述: 超精密16位格雷碼絕對編碼器模塊
文件頁數(shù): 7/8頁
文件大?。?/td> 231K
代理商: AEAS-7500
7
Figure 5. Schematic for using AEAS-7500
Using the AEAS-7500
IMPORTANT NOTE: The RC-filter combination, especially on
VDDA, is used to filter spikes and transients and is strongly
recommended. It is advised that the tantalum caps be put
as close to the VDD and VDDA pins as possible.
It is recommended to ground the PROBE_ON pin during
normal operation.
Leave PCL unconnected. A09N and A0N are the negative
cosine and sine waves, the negative versions of A09P and
A0P.
D0 is used to check the D0 signal. D0 is the digitized signal
of A0. DPROBE is used to check D09, the digitized signal of
A09. Recommended to be used for testing purpose only.
KORR is for Gray Code correction for 12 bits resolution
only.
MSBINV is for user to change between counting up and
counting down for a given rotating direction. MSB(D11)
will always be sent out to DOUT first
LEDR is an internal voltage monitor which is linked to the
Monitor channel. It should be connected to the base of an
NPN transistor via a series resistor to control the LED bright-
ness per the photodiodes’ need. (Refer to Figure 5)
LERR will be high when the light output perceived by the
photo diode array is low, and the LED current is under
overdrive mode. This is an indicator when light intensity is
at a critical stage affecting the performance of the encoder.
It is caused either by contamination of the codewheel or
LED degradation.
Operation
After powering up the unit using VD =+5V and con-
necting GND to ground, trigger input pins NSL and SCL
using the timing diagram (Figure 4). NSL is a control pin
for the internal shift register. NSL=1 is load mode while
NSL=0 is shift mode for the shift register. When NSL=0
and combined with clock pulses, the serial Gray code will
be shifted out to DOUT bit by bit per every clock pulse.
Valid data of DOUT should be sampled at the low point
of the clock pulses.
The 16 bit serial gray code can be tapped out from pin
DOUT, most significant bit (D11) first. The rate of the
16bit Gray code serial transfer rate is dependent on the
SCL clock frequency. The faster the clock, the faster the
transfer rate. The maximum clock rate the AEAS-7500 can
take is 16 MHz, which means the entire 16 bit Gray code
can be serially transferred out in 1 us.
Whenever NSL is high (load mode), the DOUT will have the
logic of the MSB (D11). After NSL goes low, the number of
bits being transferred out will depend on the number of
clock pulses given to SCL. The default is 16 clock pulses
for the 16 bit Gray code.
A
MSBINV
PCL
PROBE_ON
KORR
LERR
LERR
D0
10R
min 100μ
Tantal
0R to R
Tantal
min μ
VDD
VDD
(C's optional)
DIN
NSL
SCL
DOUT
GND
VD
GND
VD (+V)
A
KORR
PROBE_ON
A09N
GND
VDDA
A0P
A0N
A09P
LEDR
PCL
MSBINV
DOUT
SCL
DIN
NSL
VDD
DPROBE
D0
D09
Configuration
and
Probe Control
STCAL
STCAL
IR-LED
7R
BC86B
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