6
Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.
BIT
ERROR
RATE
-6
4
1 x 10 -2
RELATIVE INPUT OPTICAL POWER - dB
-4
2
-2
0
1 x 10 -4
1 x 10 -6
1 x 10 -8
1 x 10 -10
1 x 10 -11
CONDITIONS:
1. 125 MBd
2. PRBS 2 7-1
3. CENTER OF SYMBOL SAMPLING
4. T
A = +25 C
5. V
CC = 3.3 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/ 2.1 ns.
1 x 10 -12
1 x 10 -9
1 x 10 -7
1 x 10 -5
1 x 10 -3
CENTER OF SYMBOL
HFBR-5903 SERIES
Figure 5. Transceiver Relative Optical Power Budget at Constant BER vs.
Signaling Rate.
CONDITIONS:
1. PRBS 2 7-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
4. TA= +25 C
5. VCC= 3.3 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/ 2.1 ns.
-1
-0.5
0
0.5
1
1.5
2
2.5
0
25
50
75
100
125
150
175
200
SIGNAL RATE (MBd)
TRANSCEIVER
RELATIVE
POWER
BUDGE
T
AT
CONSTANT
BER
(dB)
Transceiver Signaling Operating Rate Range and BER
Performance
Forpurposesofdefinition,thesymbol(Baud)rate,also
called signaling rate, is the reciprocal of the shortest
symbol time. Data rate (bits/sec) is the symbol rate di-
vided by the encoding factor used to encode the data
(symbols/bit).
WhenusedinFDDIandATM100Mb/sapplicationsthe
performanceofthe1300nmtransceiversisguaranteed
overthesignalingrateof10MBdto125MBdtothefullcon-
ditionslistedinindividualproductspecificationtables.
The transceivers may be used for other applications at
signalingratesoutsideofthe10MBdto125MBdrange
withsomepenaltyinthelinkopticalpowerbudgetpri-
marilycausedbyareductionofreceiversensitivity.Figure
5givesanindicationofthetypicalperformanceofthese
1300nmproductsatdifferentrates.
Thesetransceiverscanalsobeusedforapplicationswhich
requiredifferentBitErrorRate(BER)performance.Figure
6illustratesthetypicaltrade-offbetweenlinkBERandthe
receiversinputopticalpowerlevel.
Transceiver Jitter Performance
TheAvagoTechnologies1300nmtransceiversaredesigned
tooperateperthesystemjitterallocationsstatedinTable
E1ofAnnexEoftheFDDIPMDandLCF-PMDstandards.
TheAvagoTechnologies1300nmtransmitterswilltolerate
theworstcaseinputelectricaljitterallowedinthesetables
withoutviolatingtheworstcaseoutputjitterrequirements
ofSections8.1ActiveOutputInterfaceoftheFDDIPMD
andLCF-PMDstandards.
TheAvagoTechnologies1300nmreceiverswilltoleratethe
worstcaseinputopticaljitterallowedinSections8.2Active
InputInterfaceoftheFDDIPMDandLCF-PMDstandards
withoutviolatingtheworstcaseoutputelectricaljitter
allowedinTableE1ofAnnexE.
Thejitterspecificationsstatedinthefollowing1300nm
transceiverspecificationtablesarederivedfromthevalues
inTableE1ofAnnexE.Theyrepresenttheworstcasejitter
contribution that the transceivers are allowed to make
totheoverallsystemjitterwithoutviolatingtheAnnexE
allocationexample.Inpracticethetypicalcontributionof
theAvagoTechnologiestransceiversiswellbelowthese
maximumallowedamounts.
Recommended Handling Precautions
Avago Technologies recommends that normal static
precautions be taken in the handling and assem-
bly of these transceivers to prevent damage which
may be induced by electrostatic discharge (ESD).
TheAFBR-5903ZseriesoftransceiversmeetMIL-STD-883C
Method3015.4Class2products.
Careshouldbeusedtoavoidshortingthereceiverdataor
signaldetectoutputsdirectlytogroundwithoutproper
currentlimitingimpedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugsinsertedintotheMT-RJconnectorreceptacle.This
processplugprotectstheopticalsubassembliesduring
wavesolderandaqueouswashprocessingandactsasa
dustcoverduringshipping.
These transceivers are compatible with either industry
standardwaveorhandsolderprocesses.
Shipping Container
Thetransceiverispackagedinashippingcontainerde-
signed to protect it from mechanical and ESD damage
duringshipmentorstorage.