參數(shù)資料
型號: AFCT-57V6USZ
元件分類: 光收發(fā)
英文描述: FIBER OPTIC TRANSCEIVER, 1270-1600nm, 1250Mbps(Tx), 1250Mbps(Rx), BOARD/PANEL MOUNT, LC CONNECTOR
封裝: ROHS COMPLIANT, DIP-20
文件頁數(shù): 19/22頁
文件大?。?/td> 508K
代理商: AFCT-57V6USZ
6
Figure 3. SFP Transceiver Electrical Pad Layout
VeeT
TD-
TD+
VeeT
VccT
VccR
VeeR
RD+
RD-
VeeR
20
19
18
17
16
15
14
13
12
11
VeeT
TX_FAULT
TX_DISABLE
RX_LOS
VeeR
1
2
3
4
5
6
7
8
9
10
Top of Board
Bottom of Board
(as view through top of board)
RATE_SELECT
MOD_DEF[0]
MOD_DEF[1]
MOD_DEF[2]
Hot-Plugging Sequence
The ground, VCC and other pins designated as the se-
quence (1) pins engage first during hot-plugging. The
sequence (2) pins connect second during hot-plugging
followed by the sequence (3) pins. Conversely, when
the module is unplugged from the host system, the se-
quence (3) pins disengages before the sequence (2) pins
disengages and then followed by the sequence (1) pins.
Inserting or removing the AFCT-57V6USZ will disrupt
data transmission. This disruption occurs when the
downstream receiver (e.g. deserializer phase-lock-loop)
resynchronizes to a different bitstream signal. When this
occurs, the downstream system will recognize the asso-
ciated error (e.g. comma detect, loss-of-light, disparity,
CRC, and frame errors).
It is the responsibility of the system integrator to assure
that no thermal, energy, or voltage hazard exists during
the hot-plug-unplug sequence. It is also the responsibility
of the system integrator and end-user to minimize static
electricity and the probability of ESD events by careful
design.
Pin Description
A brief description of all of the electrical connector pins follows. The connector has staged contacts, so that hot-plug-
ging can be performed. See Table 10.
Table 10. Pinout.
Pin No.
Sequence
Description
Pin No
Sequence
Description
1
VeeT
11
1
VeeR
2
3
TX_FAULT
12
3
RD-
3
TX_DISABLE
13
3
RD+
4
3
MOD_DEF[2]
14
1
VeeR
5
3
MOD_DEF[1]
15
2
VccR
6
3
MOD_DEF[0]
16
2
VccT
7
3
RATE_SELECT
17
1
VeeT
8
3
RX_LOS
18
3
TD+
9
1
VeeR
19
3
TD-
10
1
VeeR
20
1
VeeT
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