10
adequate size to minimize resistive losses, and that a
good quality capacitor of approximately 100fd be
connected directly across the input terminals to assure
an adequately low impedance at the input terminals.
Table I relates nominal resistance values and selected
wire sizes.
Table I. Nominal Resistance Of Cu Wire
Wire Size, AWG
Resistance per ft
24 Ga
25.7 m
22 Ga
16.2 m
20 Ga
10.1 m
18 Ga
6.4 m
16 Ga
4.0 m
14 Ga
2.5 m
12 Ga
1.6 m
As an example of the effects of parasitic resistance,
consider an AFL2815S operating at full power of 120
W. From the specification sheet, this device has a
minimum efficiency of 83% representing an input
power of nearly 145 W. If we consider the case where
line voltage is at its’ minimum of 16 volts, the steady
state input current necessary for this example will be
slightly greater than 9 amperes. If this device were
connected to a voltage source with 10 feet of 20 gauge
wire, the round trip (input and return) would result in 0.2
of resistance and 1.8 volts of drop from the source
to the converter. To assure 16 volts at the input, a
source closer to 18 volts would be required.
In
applications using the paralleling option, this drop will be
multiplied by the number of paralleled devices. By
choosing 14 or 16 gauge wire in this example the
parasitic resistance and resulting voltage drop will be
reduced to 25% or 31% of that with 20 gauge wire.
Another potential problem resulting from parasitically
induced voltage drop on the input lines is with regard to
operation of the enable 1 port. The minimum and
maximum operating levels required to operate this port
are specified with respect to the input common return
line at the converter. If a logic signal is generated with
respect to a ‘common’ that is distant from the con-
verter, the effects of the voltage drop over the return line
must be considered when establishing the worst case
TTL switching levels. These drops will effectively
impart a shift to the logic levels. In Figure VI, it can be
seen that referred to system ground, the voltage on the
input return pin is given by
e
Rtn = IRtn Rp
Therefore, the logic signal level generated in the system
must be capable of a TTL logic high plus sufficient
additional amplitude to overcome e
Rtn.
When the con-
verter is inhibited, I
Rtn diminishes to near zero and eRtn
will then be at system ground.
Incorporation of a 100 fd capacitor at the input
terminals is recommended as compensation for the
dynamic effects of the parasitic resistance of the
input cable reacting with the complex impedance of
the converter input, and to provide an energy reser-
voir for transient input current requirements.
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
R
p
R
p
I
Rtn
I
in
e
source
System Ground
e
Rtn
100
fd
Figure VI. Effects of Parasitic Resistance in Input Leads