Revision 23 2-43 Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-51 3.3 V LVTTL / 3.3 V" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGL060V5-VQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 206/250闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA IGLOO 1.5V 100VQFP IND
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1536
RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€(m茅n)鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
鍏跺畠鍚嶇ū(ch膿ng)锛� 1100-1087
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IGLOO Low Power Flash FPGAs
Revision 23
2-43
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-51 3.3 V LVTTL / 3.3 V LVCMOS Low Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
0.97
4.47 0.18 0.85
0.66
4.56 3.89 2.24 2.19
8.15
7.48
ns
6 mA
Std.
0.97
3.74 0.18 0.85
0.66
3.82 3.37 2.49 2.63
7.42
6.96
ns
8 mA
Std.
0.97
3.74 0.18 0.85
0.66
3.82 3.37 2.49 2.63
7.42
6.96
ns
12 mA
Std.
0.97
3.23 0.18 0.85
0.66
3.30 2.98 2.66 2.91
6.89
6.57
ns
16 mA
Std.
0.97
3.08 0.18 0.85
0.66
3.14 2.89 2.70 2.99
6.74
6.48
ns
24 mA
Std.
0.97
3.00 0.18 0.85
0.66
3.06 2.91 2.74 3.27
6.66
6.50
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-52 3.3 V LVTTL / 3.3 V LVCMOS High Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive Strength
Speed Grade
tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ tZLS tZHS Units
4 mA
Std.
0.97
2.73 0.18 0.85
0.66
2.79 2.22 2.25 2.32 6.38 5.82
ns
6 mA
Std.
0.97
2.32 0.18 0.85
0.66
2.37 1.85 2.50 2.76 5.96 5.45
ns
8 mA
Std.
0.97
2.32 0.18 0.85
0.66
2.37 1.85 2.50 2.76 5.96 5.45
ns
12 mA
Std.
0.97
2.09 0.18 0.85
0.66
2.14 1.68 2.67 3.05 5.73 5.27
ns
16 mA
Std.
0.97
2.05 0.18 0.85
0.66
2.10 1.64 2.70 3.12 5.69 5.24
ns
24 mA
Std.
0.97
2.07 0.18 0.85
0.66
2.12 1.60 2.75 3.41 5.71 5.20
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-53 3.3 V LVTTL / 3.3 V LVCMOS Low Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus Banks
Drive Strength
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
Std.
0.97
3.94 0.18 0.85
0.66
4.02 3.46 1.98 2.03
7.62
7.05
ns
6 mA
Std.
0.97
3.24 0.18 0.85
0.66
3.31 2.99 2.21 2.42
6.90
6.59
ns
8 mA
Std.
0.97
3.24 0.18 0.85
0.66
3.31 2.99 2.21 2.42
6.90
6.59
ns
12 mA
Std.
0.97
2.76 0.18 0.85
0.66
2.82 2.63 2.36 2.68
6.42
6.22
ns
16 mA
Std.
0.97
2.76 0.18 0.85
0.66
2.82 2.63 2.36 2.68
6.42
6.22
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
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