參數(shù)資料
型號(hào)： AGL10002-FGG144
元件分類(lèi)： FPGA
英文描述： FPGA, 1000000 GATES, 200 MHz, PBGA144
封裝： 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144
文件頁(yè)數(shù)： 188/204頁(yè)
文件大?。?/td> 2800K
代理商： AGL10002-FGG144
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
3- 4
A dvanced v0. 1
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and
Industrial)
Sophisticated
power-up
management
circuitry
is
designed into every IGLOO device. These circuits ensure
easy transition from the powered-off state to the
powered-up state of the device. The many different
supplies can power up in any sequence with minimized
current spikes or surges. In addition, the I/O will be in a
known state through the power-up sequence. The basic
principle is shown in Figure 3-1.
There are five regions to consider during power-up.
IGLOO I/Os are activated only if ALL of the following
three conditions are met:
1. VCC and VCCI are above the minimum specified trip
points (Figure 3-1).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV
higher than ramp-down trip points. This specifically
built-in
hysteresis
prevents
undesirable
power-up
oscillations and current surges. Note the following:
During programming, I/Os become tristated and
weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump
VPUMP supply have no influence on I/O behavior.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input
buffer activation
To make sure the transition from input buffers to output
buffers is clean, ensure that there is no path longer than
100 ns from input buffer to output buffer in your
design.
Figure 3-1
I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because V
CCI
/V
CC
are below
specification. For the same reason, input
buffers do not meet V
IH
/V
IL
levels, and
output buffers do not meet V
OH
/V
OL
levels.
Min V
CCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
Va = 0.85 V ± 0.25 V
Deactivation trip point:
Vd = 0.75 V ± 0.25 V
Activation trip point:
Va = 0.9 V ± 0.3 V
Deactivation trip point:
Vd = 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, V
IH
/V
IL
, V
OH
/V
OL
, etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because V
CCI is
below specification. For the
same reason, input buffers do not
meet V
IH
/V
IL
levels, and output
buffers do not meet V
OH
/V
OL
levels.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the V
CC
is below specification.
V
CC = VCCI + VT
相關(guān)PDF資料
PDF描述
AGL10002-FGG256I FPGA, 1000000 GATES, 200 MHz, PBGA144
AGL10002-FGG256 FPGA, 1000000 GATES, 200 MHz, PBGA144
AGL10002-FGG484I FPGA, 1000000 GATES, 200 MHz, PBGA484
AGL10002-FGG484 FPGA, 1000000 GATES, 200 MHz, PBGA484
AGL10005-FFG144I FPGA, 1000000 GATES, 250 MHz, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGL1000V2-CS144 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144ES 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144I 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144PP 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS281 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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