參數(shù)資料
型號(hào)： AGL10005-FFGG144I
元件分類： FPGA
英文描述： FPGA, 1000000 GATES, 250 MHz, PBGA144
封裝： 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144
文件頁(yè)數(shù)： 136/204頁(yè)
文件大?。?/td> 2800K
代理商： AGL10005-FFGG144I
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)當(dāng)前第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-23
SRAM and FIFO3
IGLOO devices (AGL250, AGL600, and AGL1000) have
embedded SRAM blocks along their north and south
sides; AGL060 and AGL125 devices have embedded
SRAM blocks on the north side only. The AGL030 does
not include SRAM or FIFO. To meet the needs of high-
performance designs, the memory blocks operate strictly
in
synchronous
mode
for
both
read
and
write
operations. The read and write clocks are completely
independent, and each may operate at any desired
frequency up to 250 MHz.
4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—2 read,
2 write or 1 read, 1 write)
512×9, 256×18 (2-port RAM—1 read and 1 write)
Sync write, sync pipelined / nonpipelined read
The IGLOO memory block includes dedicated FIFO
control logic to generate internal addresses and external
flag
logic
(FULL,
EMPTY,
AFULL,
AEMPTY).
Block
diagrams of the memory modules are illustrated in
Simultaneous
dual-port
read/write
and
write/write
operations at the same address are allowed when certain
timing requirements are met.
During RAM operation, addresses are sourced by the
user logic and the FIFO controller is ignored. In FIFO
mode, the internal addresses are generated by the FIFO
controller and routed to the RAM array by internal
MUXes. Refer to Figure 2-23 on page 2-25 for more
information about the implementation of the embedded
FIFO controller.
The IGLOO architecture enables the read and write sizes
of RAMs to be organized independently, allowing for
bus conversion. For example, the write side size can be
set to 256×18 and the read size to 512×9.
Both the write width and read width for the RAM blocks
can be specified independently with the WW (write
width) and RW (read width) pins. The different D×W
configurations are: 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
Refer to the allowable RW and WW values supported for
each of the RAM macro types in Table 2-6 on page 2-26.
When widths of one, two, or four are selected, the ninth
bit is unused. For example, when writing nine-bit values
and reading four-bit values, only the first four bits and
the second four bits of each nine-bit value are
addressable for read operations. The ninth bit is not
accessible.
Conversely, when writing four-bit values and reading
nine-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte
order for read and write operations.
3. The AGL030 device does not support SRAM or FIFO.
相關(guān)PDF資料
PDF描述
AGL10005-FFGG144 FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFGG256I FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFGG256 FPGA, 1000000 GATES, 250 MHz, PBGA144
AGL10005-FFGG484I FPGA, 1000000 GATES, 250 MHz, PBGA484
AGL10005-FFGG484 FPGA, 1000000 GATES, 250 MHz, PBGA484
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGL1000V2-CS144 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS144PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL1000V2-CS281 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*