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參數(shù)資料
| 型號： | AGL10005-FFGG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 176/204頁 |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFGG256 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-59
Actel recommends that VPUMP and VJTAG power supplies
are kept separate with independent filtering capacitors
rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly
pulled up to VCCI. With VCCI, VMV, and VCC supplies
continuously powered up, when the device transitions
from programming to operating mode, the I/Os are
instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of high
impedance).
Input buffer is disabled (with tristate value of high
Weak pull-up is programmed.
GL
Globals
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as I/Os, since they have identical capabilities.
Unused GL pins are configured as inputs with pull-up
resistors. See more detailed descriptions of global I/O
connectivity in the "Clock Conditioning Circuits" section
on page 2-14. All inputs labeled GC/GF are direct inputs
into the quadrant clocks. For example, if GAA0 is used
for an input, GAA1 and GAA2 are no longer available for
input to the quadrant globals. All inputs labeled GC/GF
are direct input into the chip-level globals, and the rest
are connected to the quadrant globals. The inputs to the
global network are multiplexed, and only one input can
be used as a global input.
Refer to the "User I/O Naming Convention" section on
page 2-56 for an explanation of the naming of global
pins.
FF
Flash*Freeze Mode Activation Pin
The FF pin is a dedicated input pin that is used to enter
and exit Flash*Freeze mode. The FF pin is active low, has
the same characteristics as a single-ended I/O, and must
meet
the
maximum
rise
and
fall
time.
When
Flash*Freeze mode is not used in the design, the FF pin is
available as a regular I/O.
When Flash*Freeze mode is used, the FF pin must not be
left floating to avoid accidentally entering Flash*Freeze
mode. While in Flash*Freeze mode, the Flash*Freeze pin
should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended
I/O standard supported by the I/O bank in which the pin
is located, and input signal levels compatible with the I/O
standard selected. The FF pin should be treated as a
sensitive
asynchronous
signal.
When
defining
pin
placement and board layout, simultaneously switching
outputs
(SSOs)
and
their
effects
on
sensitive
asynchronous pins must be considered.
Unused FF or I/O pins are tristated with weak pull-up.
This default configuration applies to both Flash*Freeze
mode and normal operation mode. No user intervention
is required.
Table 2-32 shows the Flash*Freeze pin location on the
available packages for IGLOO devices. The Flash*Freeze
pin
location
is
independent
of
device,
allowing
migration to larger or smaller IGLOO devices while
maintaining the same pin location on the board.
Table 2-32 Flash*Freeze Pin Location in IGLOO Family
Packages (device-independent)
Package
Flash*Freeze Pin
CS196
TBD
QN132
B12
VQ100
27
FG144
L3
FG256
T3
FG484
W6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FFGG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FFGG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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