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參數資料
| 型號： | AGL10005-FG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, FBGA-144 |
| 文件頁數： | 153/204頁 |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FG256 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 38
Advanced v0.1
For boards and cards with three levels of staging, card
power supplies must have time to reach their final values
before the I/Os are connected. Pay attention to the sizing
of power supply decoupling capacitors on the card to
ensure that the power supplies are not overloaded with
capacitance.
Cards with three levels of staging should have the
following sequence:
Grounds
Powers
I/Os and other pins
For Level 3 and Level 4 compliance with the AGL030
device, cards with two levels of staging should have the
following sequence:
Grounds
Powers, I/Os, and other pins
Cold-Sparing Support
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
The AGL030 device fully supports cold-sparing, since the I/O
clamp diode is always off (see Table 2-14 on page 2-31).
For other IGLOO devices, since the I/O clamp diode is
always active, cold-sparing can be accomplished either by
employing a bus switch to isolate the device I/Os from the
rest of the system or by driving each IGLOO I/O pin to 0 V.
If the AGL030 is used in applications requiring cold-
sparing, a discharge path from the power supply to
ground should be provided. This can be done with a
discharge resistor or a switched resistor. This is necessary
because the AGL030 does not have built-in I/O clamp
diodes.
If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitance
is in parallel with the resistor). The RC time constant
should ensure full discharge of supplies before cold-
sparing functionality is required. The resistor is necessary
to ensure that the power pins are discharged to ground
every time there is an interruption of power to the
device.
I/O cold-sparing may add additional current if a pin is
configured with either a pull-up or pull-down resistor
and driven in the opposite direction. A small static
current is induced on each I/O pin when the pin is driven
to a voltage opposite to the weak pull resistor. The
current is equal to the voltage drop across the input pin
divided by the pull resistor. Refer to Table 3-38 on
page 3-27 for the specific pull resistor value for the
corresponding I/O standard.
For example, assuming an LVTTL 3.3 V input pin is
configured with a weak pull-up resistor, a current will
flow through the pull-up resistor if the input pin is
driven LOW. For LVTTL 3.3 V, the pull-up resistor is
~45 k
Ω, and the resulting current is equal to
3.3V/45k
Ω = 73 A for the I/O pin. This is true also
when a weak pull-down is chosen and the input pin is
driven HIGH. This current can be avoided by driving the
input LOW when a weak pull-down resistor is used and
driving it HIGH when a weak pull-up resistor is used.
This current draw can occur in the following cases:
In Active and Static modes:
–
Input buffers with pull-up, driven LOW
–
Input buffers with pull-down, driven HIGH
–
Bidirectional buffers with pull-up, driven LOW
–
Bidirectional buffers with pull-down, driven
HIGH
–
Output buffers with pull-up, driven LOW
–
Output buffers with pull-down, driven HIGH
–
Tristate buffers with pull-up, driven LOW
–
Tristate buffers with pull-down, driven HIGH
In Flash*Freeze mode:
–
Input buffers with pull-up, driven LOW
–
Input buffers with pull-down, driven HIGH
–
Bidirectional buffers with pull-up, driven LOW
–
Bidirectional buffers with pull-down, driven
HIGH
Electrostatic Discharge (ESD) Protection
IGLOO devices are tested per JEDEC Standard JESD22-
A114-B.
IGLOO devices contain clamp diodes at every I/O, global,
and power pad. Clamp diodes protect all device pads
against damage from ESD as well as from excessive
voltage transients.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND and its N side connected to the
pad. During operation, these diodes are normally
biased in the off state, except when transient voltage is
significantly above VCCI or below GND levels.
In AGL030, the first diode is always off. In other IGLOO
devices, the clamp diode is always on and cannot be
switched off.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-20 on page 2-39 for
more information about the I/O standards and the clamp
diode.
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
相關PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FGG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FGG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FGG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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