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參數(shù)資料
| 型號： | AGL10005-FGG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 142/204頁 |
| 文件大小： | 2800K |
| 代理商： | AGL10005-FGG144 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 28
Advanced v0.1
RAM Initialization
Each SRAM block can be individually initialized on power-
up by means of the JTAG port using the UJTAG mechanism
(refer to the "JTAG 1532" section on page 2-63). The shift
register for a target block can be selected and loaded
with the proper bit configuration to enable serial
loading. The 4,608 bits of data can be loaded in a single
operation.
Signal Descriptions for FIFO4K186
The following signals are used to configure the FIFO4K18
memory element:
WW and RW
These signals enable the FIFO to be configured in one of
the five allowable aspect ratios (Table 2-10).
WBLK and RBLK
These signals are active low and will enable the
respective ports when LOW. When the RBLK signal is
HIGH, that port’s outputs hold the previous value.
WEN and REN
Read and write enables. WEN is active low and REN is
active high by default. These signals can be configured as
active high or low.
WCLK and RCLK
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
RPIPE
This signal is used to specify pipelined read on the
output. A LOW on RPIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
RESET
This active low signal resets the control logic and forces
the output hold state registers to zero when asserted. It
does not reset the contents of the memory array
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous RESET
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-151 on page 3-100 for the
specifications.
WD
This is the input data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. When a data width
less than 18 is specified, unused higher-order signals
must be grounded (Table 2-11).
RD
This is the output data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. Like the WD bus, high-
order bits become unusable if the data width is less than
18. The output data on unused pins is undefined
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further
counting once the FIFO is empty (i.e., the EMPTY flag
goes HIGH). A HIGH on this signal inhibits the counting.
FSTOP is used to stop the FIFO write counter from further
counting once the FIFO is full (i.e., the FULL flag goes
HIGH). A HIGH on this signal inhibits the counting.
For more information on these signals, refer to the
FULL, EMPTY
When the FIFO is full and no more data can be written,
the FULL flag asserts HIGH. The FULL flag is synchronous
to WCLK to inhibit writing immediately upon detection
of a full condition and to prevent overflows. Since the
write address is compared to a resynchronized (and thus
time-delayed) version of the read address, the FULL flag
will remain asserted until two WCLK active edges after a
read operation eliminates the full condition.
When the FIFO is empty and no more data can be read,
the EMPTY flag asserts HIGH. The EMPTY flag is
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
6. The AGL030 device does not support SRAM or FIFO.
Table 2-10 Aspect Ratio Settings for WW[2:0]
WW[2:0]
RW[2:0]
D×W
000
4k×1
001
2k×2
010
1k×4
011
512×9
100
256×18
101, 110, 111
Reserved
Table 2-11 Input Data Signal Usage for Different Aspect
Ratios
D×W
WD/RD Unused
4k×1
WD[17:1], RD[17:1]
2k×2
WD[17:2], RD[17:2]
1k×4
WD[17:4], RD[17:4]
512×9
WD[17:9], RD[17:9]
256×18
–
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相關(guān)代理商/技術(shù)參數(shù) |
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| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
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