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參數(shù)資料
| 型號(hào)： | AGL10005-FGG144I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 175/204頁 |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FGG144I |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 58
Advanced v0.1
Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O
logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O
banks.
Within
the
package,
the
GNDQ
plane
is
decoupled from the simultaneous switching noise
originated from the output buffer ground domain. This
minimizes the noise transfer within the package and
improves input signal integrity. GNDQ must always be
connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V for
IGLOO V5 devices and 1.2 V or 1.5 V for IGLOO V2
devices. VCC is required for powering the JTAG state
machine in addition to VJTAG. Even when an IGLOO
device
is
in
bypass
mode
in
a
JTAG
chain
of
interconnected devices, both VCC and VJTAG must remain
powered to allow JTAG signals to pass through the
IGLOO device.
For IGLOO V2 devices, VCC can be switched dynamically
from 1.2 V to 1.5 V or vice versa. This allows in system
programming when VCC is at 1.5 V and the benefit of
low-power operation when VCC is at 1.2 V.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O
logic. Bx is the I/O bank number. There are eight I/O
banks on IGLOO devices plus a dedicated VJTAG bank.
Each bank can have a separate VCCI connection. All I/Os
in a bank will run off the same VCCIBx supply. VCCI can be
1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O
banks should have their corresponding VCCI pins tied to
GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O
bank. x is the bank number. Within the package, the
VMV
plane
is
decoupled
from
the
simultaneous
switching noise originated from the output buffer VCCI
domain. This minimizes the noise transfer within the
package and improves input signal integrity. Each bank
must have at least one VMV connection, and no VMV
should be left unconnected. All I/Os in a bank run off the
same VMVx supply. VMV is used to provide a quiet supply
voltage to the input buffers of each I/O bank. VMVx can
be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O
banks should have their corresponding VMV pins tied to
GND. VMV and VCCI should be at the same voltage within
a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0
to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLF
PLL Supply Voltage7
Supply voltage to analog PLL, nominally 1.5 V for IGLOO
V5 devices and 1.2 V or 1.5 V for IGLOO V2 devices. If
unused, VCCPLF should be tied to either the power supply
or GND.
VCOMPLF
PLL Ground7
Ground to analog PLL power supplies. Unused VCOMPLF
pins should be connected to GND.
VJTAG
JTAG Supply Voltage
IGLOO devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). Isolating the JTAG power supply
in a separate I/O bank gives greater flexibility in supply
selection and simplifies power supply and PCB design. If
the JTAG interface is neither used nor planned for use,
the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be
powered for JTAG operation; VJTAG alone is insufficient. If
an IGLOO device is in a JTAG chain of interconnected
boards, the board containing the IGLOO device can be
powered down, provided both VJTAG and VCC to the
IGLOO part remain powered; otherwise, JTAG signals will
not be able to transition the IGLOO device, even in
bypass mode.
Actel recommends that VPUMP and VJTAG power supplies
are kept separate with independent filtering capacitors
rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
IGLOO devices support single-voltage ISP programming
of
the
configuration
flash
and
FlashROM.
For
programming, VPUMP should be 3.3 V nominal. During
normal device operation, VPUMP can be left floating or
can be tied (pulled up) to any voltage between 0 V and
3.45 V. Programming power supply voltage (VPUMP)
range is 3.15 V to 3.45 V.
When the VPUMP pin is tied to ground, it will shut off the
charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 F and 0.33 F capacitors
(both rated at 16 V) are to be connected in parallel
across VPUMP and GND, and positioned as close to the
FPGA pins as possible.
7. The AGL030 device does not support this feature.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FGG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FGG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FGG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FGG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FGG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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