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參數(shù)資料
| 型號(hào)： | AGL10005-FGG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 121/204頁 |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FGG484I |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-9
Clock Resources (VersaNets)
IGLOO devices offer powerful and flexible control of
circuit timing through the use of analog circuitry. Each
chip has up to six CCCs. The west CCC also contains a
phase-locked loop (PLL) core, delay lines, a phase shifter
(0°, 90°, 180°, 270°), and clock multipliers/dividers. Each
CCC has all the circuitry needed for the selection and
interconnection of inputs to the VersaNet global
network. The east and west CCCs each have access to
three VersaNet global lines on each side of the chip (six
total lines). The CCCs at the four corners each have access
to three quadrant global lines in each quadrant of the
chip (except AGL030).
Advantages of the VersaNet Approach
One of the architectural benefits of IGLOO is the set of
powerful and low-delay VersaNet global networks.
IGLOO offers six chip (main) global networks that are
distributed from the center of the FPGA array (Figure 2-9
on page 2-10). In addition, IGLOO devices have three
regional globals in each of the four chip quadrants. Each
core VersaTile has access to nine global network
resources: three quadrant and six chip (main) global
networks, and a total of 18 globals on the device. Each of
these networks contains spines and ribs that reach all the
VersaTiles in the quadrants (Figure 2-10 on page 2-11).
This flexible VersaNet global network architecture allows
users to map up to 144 different internal/external clocks
in a IGLOO device. Details on the VersaNet networks are
given in Table 2-2 on page 2-11. The flexible use of the
IGLOO VersaNet global network allows the designer to
address several design requirements. User applications
that
are
clock-resource-intensive
can
easily
route
external or gated internal clocks using VersaNet global
routing networks. Designers can also drastically reduce
delay penalties and minimize resource usage by mapping
critical,
high-fanout
nets
to
the
VersaNet
global
network.
In AGL030 devices, all six VersaNets are driven from three
southern I/Os, located toward the east and west sides.
Each of these tiles can be configured to select a central
I/O on its respective side or an internal routed signal as
the input signal. The AGL030 does not support any clock
conditioning circuitry, nor does it contain the VersaNet
global network concept of top and bottom spines.
VersaNet Global Networks and Spine Access
The IGLOO architecture contains a total of 18 segmented
global networks that can access the VersaTiles, SRAM,
and I/O tiles of the IGLOO device. There are nine global
network resources in each device quadrant: three
quadrant globals and six chip (main) global networks.
Each device has a total of 18 globals. These VersaNet
global networks offer fast, low-skew routing resources
for high-fanout nets, including clock signals. In addition,
these highly segmented global networks offer users the
flexibility to create low-skew local networks using spines
for up to 144internal/external clocks (in an AGL1000
device) or other high-fanout nets in IGLOO devices.
Optimal usage of these low-skew networks can result in
significant improvement in design performance on
IGLOO devices.
The nine spines available in a vertical column reside in
global networks with two separate regions of scope: the
quadrant global network, which has three spines, and
the chip (main) global network, which has six spines.
Note that there are three quadrant spines in each
quadrant of the device (except for AGL030). There are
four quadrant global network regions per device
The spines are the vertical branches of the global
network tree, shown in Figure 2-11 on page 2-12. Each
spine in a vertical column of a chip (main) global
network is further divided into two equal-length spine
segments: one in the top and one in the bottom half of
the die.
Each spine and its associated ribs cover a certain area of
the IGLOO device (the "scope" of the spine; see Figure 2-9
on page 2-10). Each spine is accessed by the dedicated
global network MUX tree architecture, which defines how
a particular spine is driven—either by the signal on the
global network from a CCC, for example, or by another
net defined by the user (Figure 2-12 on page 2-13).
Quadrant spines can be driven from user I/Os on the north
and south sides of the die. The ability to drive spines in the
quadrant global networks can have a significant effect on
system performance for high-fanout inputs to a design.
Details of the chip (main) global network spine-selection
MUX are presented in Figure 2-12 on page 2-13. The
spine drivers for each spine are located in the middle of
the die.
Quadrant spines are driven from a north or south rib.
Access to the top and bottom ribs is from the corner CCC
or from the I/Os on the north and south sides of the
device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FGG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGLN030V2-FCSG81 | FPGA, PBGA81 |
| AGLN030V2-FQN48 | FPGA, PQCC48 |
| AGLN030V2-FQN68 | FPGA, PQCC68 |
| AGLN030V2-FQNG48 | FPGA, PQCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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